我在 Active-hdl 中用 verilog 编写 4 位全加器我认为我的代码和测试台是正确的，但是 sum 和 cout 的值在波形中总是 z 任何人都可以帮助我解决问题。这是我的代码和测试-bech
module fullAdder(A, B, cin, sum, cout);
input A,B,cin;
output sum,cout;
assign {cout , sum} = A + B + cin;
endmodule
module fullAdder4bits(A, B, cin, sum, cout);
input [3:0] A,B;
input cin;
output [3:0] sum;
output cout;
wire w1,w2,w3;
fullAdder I0(A[0],B[0],cin,sum[0],w1);
fullAdder I1(A[1],B[1],w1,sum[1],w2);
fullAdder I2(A[2],B[2],w2,sum[2],w3);
fullAdder I3(A[3],B[3],w3,sum[3],cout);
endmodule
`timescale 1 ns/1 ps
module testbench;
reg tcin;
reg [3:0] tA,tB;
wire [3:0] tsum;
wire tcout;
fullAdder4bits dut(tA, tB, tcin, tsum, tcout);
initial
begin
tA = 0;
tB = 0;
tcin = 0;
#10 tA = 5;
#10 tB = 8;
#10 tA = 7;
#10 tcin = 1;
end
initial $monitor("A = %d , B = %d , cin = %b , sum = %d , cout = %b",tA,tB,tcin,tsum,tcout);
initial #60 $finish;
endmodule
