我编写了一个 VHDL 函数vectorize()
来将 std_logic_vector 数组(slv_1d_array_type
在我的代码中输入)转换为 std_logic_vector。
Vivado 2018.2[Synth 8-5882] found unsupported attribute ["test_top.vhd":41]
使用以下示例生成此错误。我已将 Vivado 配置为使用 VHDL-2008。
如何使这些'length
属性起作用以避免传递数组大小?
-- Libraries
------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------------------------------------------------
entity test_top is
generic(
DATA_WIDTH : positive := 32
);
port(
O_DATA : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity test_top;
------------------------------------------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------------------------------------------
architecture rtl of test_top is
--------------------------------------------------------------------------------------------------------------------
-- Types definition
--------------------------------------------------------------------------------------------------------------------
type slv_1d_array_type is array (natural range <>) of std_logic_vector; -- One-dimensional std_logic_vector array type.
--------------------------------------------------------------------------------------------------------------------
-- Functions declaration
--------------------------------------------------------------------------------------------------------------------
function vectorize(constant SLV_1D_ARRAY : in slv_1d_array_type) return std_logic_vector is
variable vector_v : std_logic_vector(SLV_1D_ARRAY'length * SLV_1D_ARRAY'element'length - 1 downto 0);
begin
for i in SLV_1D_ARRAY'range loop
vector_v(SLV_1D_ARRAY'element'length * (i + 1) - 1 downto SLV_1D_ARRAY'element'length * i) := SLV_1D_ARRAY(i);
end loop;
return vector_v;
end function vectorize;
--------------------------------------------------------------------------------------------------------------------
-- Signals declaration
--------------------------------------------------------------------------------------------------------------------
signal data_r : slv_1d_array_type(0 to DATA_WIDTH / 8 - 1)(7 downto 0) := (others => (others => '0'));
begin
O_DATA <= vectorize(data_r);
end architecture rtl;