verilog - 为什么这个 Verilog 函数中没有 assign 语句？

Question

来自 C++ 背景，我开始学习 Verilog。该代码描述了进入两个与门的四个输入。这两个与门的输出进入或门。或门的输出是最终输出。

// a user-defined AND gate
module my_and2 (in, out);
input [1:0] in;
output out;
assign out = in[1]&in[0];
endmodule

// a user-defined OR gate
module my_or2 (in, out);
input [1:0] in;
output out;
assign out = in[1]|in[0];
endmodule

// the AND-OR logic built on top of the user-defined AND and OR gates
module and_or (in_top, out_top);
input [3:0] in_top;
output out_top;
wire [1:0] sig;
// instantiate the gate-level modules
my_and2 U1 (.in(in_top[3:2]),.out(sig[1]));
my_and2 U2 (.in(in_top[1:0]),.out(sig[0]));
my_or2 U3 (.in(sig),.out(out_top));
endmodule

前两个模块对我来说很有意义。但是，最后一个没有。前两个模块的末尾有一个 assign 语句来设置输出变量的值。但是，最后一个没有。这是为什么？

Answer 1

Verilog 是“事件驱动的”。在编写 verilog 时，请考虑敏感度列表。

In your example of the AND gate, you've the expression assign out = in[1]&in[0];. Your expression is said to be sensitive to in[0] and in[1]. This means that any time in[0] or in[1] change, the expression will be recomputed, and the value of out will be updated.

So in your toplevel module and_or, you're basically building a big tree of expressions that are sensitive to the outputs of the preceding expressions. This tree is, of course, built using the module connections. So a change in the value of one of the inputs to this toplevel module will ripple through all expressions in its 'logic cone'.

To drive the inputs you'll need higher level testbench module driving signals into your and_or module. This will supply inputs spaced out in time which will trigger the expressions in and below and_or. If not, your sim will have no events, so no expressions will trigger and the sim will time-out at 0ps because it is 'event starved'.

PS: for your AND gate expression, assign out = ∈ will work too... (reduction AND operator)

Answer 2

out_top 由 U3 实例输出驱动。

Answer 3

To put things simply, I like to think instantiation as just connecting wires.

Modules are blocks of digital circuits. You AND and OR gate modules are where magic happens. You already understand that part. By instantiating those modules, it's like you're connecting the input wires of your top level module with inputs of two blocks AND module. Then taking the outputs of them and taping them to the input wire sticking out of your OR block. And finally you're connecting the output of OR block to the output signal wire of top level.