我对来自http://langster1980.blogspot.com/2015/09/more-on-seven-segment-displays-and.html的代码片段有疑问
我的代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity main is
port (
clock_in : in std_logic;
Seven_Segment_Enable : out std_logic_vector(2 downto 0);
Seven_Segment_Display : out std_logic_vector(7 downto 0)
);
end main;
architecture Behavioral of main is
signal refresh_count : integer := 0;
signal refresh_clk : std_logic := '1';
signal second_count : integer := 0;
signal second_clk : std_logic := '1';
signal digit_sel : unsigned(1 downto 0);
signal bcd : integer := 0;
signal Seven_Segment_Display_output : std_logic_vector (7 downto 0) := (others => '0');
signal bcd0, bcd1, bcd2 : integer := 0;
signal unit_count : integer := 0;
signal ten_count : integer := 0;
signal hundred_count : integer := 0;
begin
process(Clock_in)
begin
if(clock_in'event and clock_in='1') then
refresh_count <= refresh_count+1;
second_count <= second_count+1;
if(second_count = 750000) then
second_clk <= not second_clk;
second_count <= 1;
end if;
if(refresh_count = 1200) then
refresh_clk <= not refresh_clk;
refresh_count <= 1;
end if;
end if;
end process;
process(second_clk)
begin
if(second_clk'event and second_clk='1') then
bcd0 <= 0;
bcd1 <= 1;
bcd2 <= 2;
end if;
end process;
process(refresh_clk)
begin
if(refresh_clk' event and refresh_clk='1') then
digit_sel <= digit_sel + 1;
end if;
end process;
with digit_sel select
bcd <= bcd0 when "00",
bcd1 when "01",
bcd2 when others;
with digit_sel select
Seven_Segment_Enable <= "110" when "00",
"101" when "01",
"011" when others;
with bcd select
Seven_Segment_Display_output(7 downto 0) <= B"00000011" when 0,
B"11110011" when 1,
B"00100101" when 2,
B"01100001" when 3,
B"11010001" when 4,
B"01001001" when 5,
B"00001001" when 6,
B"11100011" when 7,
B"00000001" when 8,
B"01000001" when 9,
B"11111111" when others;
Seven_Segment_Display(7 downto 0) <= Seven_Segment_Display_output(7 downto 0);
end Behavioral;
我的问题是在显示器上绘制。根据代码应该是012号，但我的结果是
（点击放大）
而且我不知道如何解决它。你不知道该怎么办？
对不起，我的英语不好。