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I'm new to coding verilog.

This is code for a 3-bit Comparator. I need help adding a signal called 'US' (unsigned/signed) to my testbench code. When the signal is High(unsigned mode), the Comparator interprets the numbers as Unsigned numbers. When the signal is Low (Signed Mode), the Comparator interprets the numbers as signed numbers. 

module comparator(A,B,G,E,L,US);
  input [2:0]A;
  input [2:0]B;
  input US;
  output G,E,L;

  reg G,E,L;

  always@(*)
  begin
    if(US==0)
      begin

        L=$signed(A)<$signed(B);
        E=$signed(A)==$signed(B);
        G=$signed(A)>$signed(B);
      end
    else 
        L = A < B;
        E = A==B;
        G = A > B;
    end  
endmodule

TEST BENCH CODE:

`timescale 1ns /1ps
module comparator_tb();
  reg [2:0]A=3'b000;
  reg [2:0]B=3'b000;
  reg US;
  wire G,E,L;
  integer i,j;

  comparator uut(A,B,G,E,L,US);

  initial begin 

    for(i=0;i<8;i=i+1) 
      begin 
        for(j=0;j<8;j=j+1)
          begin
           #50
           B=B+1;
           end
        A = A+1;
        B=3'b000;   
      end
  #100
  $stop;
  end
endmodule
4

1 回答 1

0

我猜你想在你的测试台上切换美国。类似于以下内容？

由于 US 被声明为wire（默认），因此您需要以下assign语句：

integer us_count;
assign US = us_count;

initial begin 
 for(us_count = 0; us_count < 1; us_count++) begin
  for(i=0;i<8;i=i+1) 
  begin 
    for(j=0;j<8;j=j+1)
      begin
       #50
       B=B+1;
       end
    A = A+1;
    B=3'b000;   
  end
 end
 #100
 $stop;
end

如果将其声明为reg，则可以直接在循环中使用它而不是 us_count 并且不需要assign

reg US;
initial begin 
  for (US = 0; US < 1; US++)
  ...

其余的取决于你想如何测试它。

于 2018-04-20T21:01:15.067 回答