1

我有这个程序，我想为这个图 4x2 解码器图制作：我一直试图通过否定它们来将输出数组的初始值从 0 更改为 1 和 1 到 0，但我仍然没有得到想要的结果。

4x1 多路复用器

module DecoderMod(s, o); // module definition
   input [1:0] s;
   output [0:3] o;

   assign o[0] = s[1]; //
   assign o[1] = s[1];// 
   assign o[2] = s[0];// 
   assign o[3] = s[0];// 

endmodule

module MuxMod(s, d, o);
   input [1:0] s;
   input [0:3] d;
   output o;

   wire [0:3] s_decoded, and_out;

   DecoderMod my_decoder(s, s_decoded); // create instance

   and(and_out[0], d[0], s_decoded[0]);
   and(and_out[1], d[1], s_decoded[1]);
   and(and_out[2], d[2], s_decoded[2]);
   and(and_out[3], d[3], s_decoded[3]);
   or(o, and_out[0], and_out[1], and_out[2], and_out[3]);
endmodule

module TestMod;
   reg [1:0] s;
   reg [0:3] d;
   wire o;

   MuxMod my_mux(s, d, o);

   initial begin
      $display("Time  s   d     o");
      $display("-----------------");
      $monitor("%04d  %b  %b  %b", $time, s, d, o);
   end

   initial begin
      s[1] = 0; s[0] = 0; d = 4'b0000; #1;
      s[1] = 0; s[0] = 0; d = 4'b0001; #1;
      s[1] = 0; s[0] = 0; d = 4'b0010; #1;
      s[1] = 0; s[0] = 0; d = 4'b0011; #1;
      s[1] = 0; s[0] = 0; d = 4'b0100; #1;
      s[1] = 0; s[0] = 0; d = 4'b0101; #1;
      s[1] = 0; s[0] = 0; d = 4'b0110; #1;
      s[1] = 0; s[0] = 0; d = 4'b0111; #1;
      s[1] = 0; s[0] = 0; d = 4'b1000; #1;
      s[1] = 0; s[0] = 0; d = 4'b1001; #1;
      s[1] = 0; s[0] = 0; d = 4'b1010; #1;
      s[1] = 0; s[0] = 0; d = 4'b1011; #1;
      s[1] = 0; s[0] = 0; d = 4'b1100; #1;
      s[1] = 0; s[0] = 0; d = 4'b1101; #1;
      s[1] = 0; s[0] = 0; d = 4'b1110; #1;
      s[1] = 0; s[0] = 0; d = 4'b1111; #1;
      s[1] = 0; s[0] = 1; d = 4'b0000; #1;
      s[1] = 0; s[0] = 1; d = 4'b0001; #1;
      s[1] = 0; s[0] = 1; d = 4'b0010; #1;
      s[1] = 0; s[0] = 1; d = 4'b0011; #1;
      s[1] = 0; s[0] = 1; d = 4'b0100; #1;
      s[1] = 0; s[0] = 1; d = 4'b0101; #1;
      s[1] = 0; s[0] = 1; d = 4'b0110; #1;
      s[1] = 0; s[0] = 1; d = 4'b0111; #1;
      s[1] = 0; s[0] = 1; d = 4'b1000; #1;
      s[1] = 0; s[0] = 1; d = 4'b1001; #1;
      s[1] = 0; s[0] = 1; d = 4'b1010; #1;
      s[1] = 0; s[0] = 1; d = 4'b1011; #1;
      s[1] = 0; s[0] = 1; d = 4'b1100; #1;
      s[1] = 0; s[0] = 1; d = 4'b1101; #1;
      s[1] = 0; s[0] = 1; d = 4'b1110; #1;
      s[1] = 0; s[0] = 1; d = 4'b1111; #1;
      s[1] = 1; s[0] = 0; d = 4'b0000; #1;
      s[1] = 1; s[0] = 0; d = 4'b0001; #1;
      s[1] = 1; s[0] = 0; d = 4'b0010; #1;
      s[1] = 1; s[0] = 0; d = 4'b0011; #1;
      s[1] = 1; s[0] = 0; d = 4'b0100; #1;
      s[1] = 1; s[0] = 0; d = 4'b0101; #1;
      s[1] = 1; s[0] = 0; d = 4'b0110; #1;
      s[1] = 1; s[0] = 0; d = 4'b0111; #1;
      s[1] = 1; s[0] = 0; d = 4'b1000; #1;
      s[1] = 1; s[0] = 0; d = 4'b1001; #1;
      s[1] = 1; s[0] = 0; d = 4'b1010; #1;
      s[1] = 1; s[0] = 0; d = 4'b1011; #1;
      s[1] = 1; s[0] = 0; d = 4'b1100; #1;
      s[1] = 1; s[0] = 0; d = 4'b1101; #1;
      s[1] = 1; s[0] = 0; d = 4'b1110; #1;
      s[1] = 1; s[0] = 0; d = 4'b1111; #1;
      s[1] = 1; s[0] = 1; d = 4'b0000; #1;
      s[1] = 1; s[0] = 1; d = 4'b0001; #1;
      s[1] = 1; s[0] = 1; d = 4'b0010; #1;
      s[1] = 1; s[0] = 1; d = 4'b0011; #1;
      s[1] = 1; s[0] = 1; d = 4'b0100; #1;
      s[1] = 1; s[0] = 1; d = 4'b0101; #1;
      s[1] = 1; s[0] = 1; d = 4'b0110; #1;
      s[1] = 1; s[0] = 1; d = 4'b0111; #1;
      s[1] = 1; s[0] = 1; d = 4'b1000; #1;
      s[1] = 1; s[0] = 1; d = 4'b1001; #1;
      s[1] = 1; s[0] = 1; d = 4'b1010; #1;
      s[1] = 1; s[0] = 1; d = 4'b1011; #1;
      s[1] = 1; s[0] = 1; d = 4'b1100; #1;
      s[1] = 1; s[0] = 1; d = 4'b1101; #1;
      s[1] = 1; s[0] = 1; d = 4'b1110; #1;
      s[1] = 1; s[0] = 1; d = 4'b1111;
    end
endmodule

我的运行时输出假设与此相同： http ://athena.ecs.csus.edu/~changw/137/prg/2/demo/mux4x1-output.txt （或此处的代码）

Time s  d       o
-----------------------------
0   00  0000    0
1   00  0001    0
2   00  0010    0
3   00  0011    0
4   00  0100    0
5   00  0101    0
6   00  0110    0
7   00  0111    0
8   00  1000    1
9   00  1001    1
10  00  1010    1
11  00  1011    1
12  00  1100    1
13  00  1101    1
14  00  1110    1
15  00  1111    1
16  01  0000    0
17  01  0001    0
18  01  0010    0
19  01  0011    0
20  01  0100    1
21  01  0101    1
22  01  0110    1
23  01  0111    1
24  01  1000    0
25  01  1001    0
26  01  1010    0
27  01  1011    0
28  01  1100    1
29  01  1101    1
30  01  1110    1
31  01  1111    1
32  10  0000    0
33  10  0001    0
34  10  0010    1
35  10  0011    1
36  10  0100    0
37  10  0101    0
38  10  0110    1
39  10  0111    1
40  10  1000    0
41  10  1001    0
42  10  1010    1
43  10  1011    1
44  10  1100    0
45  10  1101    0
46  10  1110    1
47  10  1111    1
48  11  0000    0
49  11  0001    1
50  11  0010    0
51  11  0011    1
52  11  0100    0
53  11  0101    1
54  11  0110    0
55  11  0111    1
56  11  1000    0
57  11  1001    1
58  11  1010    0
59  11  1011    1
60  11  1100    0
61  11  1101    1
62  11  1110    0
63  11  1111    1

但我明白了......我做错了什么？

Time  s   d     o
-----------------
0000  00  0000  0
0001  00  0001  0
0002  00  0010  0
0003  00  0011  0
0004  00  0100  0
0005  00  0101  0
0006  00  0110  0
0007  00  0111  0
0008  00  1000  0
0009  00  1001  0
0010  00  1010  0
0011  00  1011  0
0012  00  1100  0
0013  00  1101  0
0014  00  1110  0
0015  00  1111  0
0016  01  0000  0
0017  01  0001  1
0018  01  0010  1
0019  01  0011  1
0020  01  0100  0
0021  01  0101  1
0022  01  0110  1
0023  01  0111  1
0024  01  1000  0
0025  01  1001  1
0026  01  1010  1
0027  01  1011  1
0028  01  1100  0
0029  01  1101  1
0030  01  1110  1
0031  01  1111  1
0032  10  0000  0
0033  10  0001  0
0034  10  0010  0
0035  10  0011  0
0036  10  0100  1
0037  10  0101  1
0038  10  0110  1
0039  10  0111  1
0040  10  1000  1
0041  10  1001  1
0042  10  1010  1
0043  10  1011  1
0044  10  1100  1
0045  10  1101  1
0046  10  1110  1
0047  10  1111  1
0048  11  0000  0
0049  11  0001  1
0050  11  0010  1
0051  11  0011  1
0052  11  0100  1
0053  11  0101  1
0054  11  0110  1
0055  11  0111  1
0056  11  1000  1
0057  11  1001  1
0058  11  1010  1
0059  11  1011  1
0060  11  1100  1
0061  11  1101  1
0062  11  1110  1
0063  11  1111  1
4

3 回答 3

1

我假设“DecoderMod”应该是您在几个小时前询问的 2x4 解码器。你所拥有的不是解码器，只是两根线成对连接到四个输出。

于 2018-02-25T10:46:11.397 回答
0

您的编码风格混淆了您尝试编写的逻辑。您不必要地拆分了设计，以生成 {1,1,0,0} 扩展，然后在有更简单的方法时编写实例化门。

你写过

out = ((d[0] | d[1]) & s[1]) | ((d[2] | d[3]) & s[0]);

这一行可能也不太容易阅读（我通常会将每个乘积总和项分成单独的行，但这里的括号会搞砸）但至少所有代码都在一个地方，而不是散布超过30行左右...

原来的结构可能看起来更可取的另一个原因是尽量减少逻辑并避免重复。实际上，现代（即自 2005-2010 年以来）编译器在优化逻辑方面非常聪明，特别是映射到各种奇怪的标准单元。标准单元通常有几个输入（和/或/反转排列），有时还有正常和反转输出。防止这种优化的方法之一是将特定逻辑放置在模块中，并防止跨该边界进行展平/优化。

于 2018-02-25T19:39:06.297 回答
0

使用 RTL 的简单多路复用器，更易于阅读和理解。

鉴于，

input [1:0] x_in;
output [3:0] x_out_v;

assign x_out_v [0] =  ( ~x_in[1] && ~x_in[0] ); 
assign x_out_v [1] =  ( ~x_in[1] &&  x_in[0] ); 
assign x_out_v [2] =  ( x_in[1] &&  ~x_in[0] ); 
assign x_out_v [3] =  ( x_in[1] &&   x_in[0] );
于 2018-04-01T04:38:59.290 回答