我不明白为什么在使用 model-sim 时会出现此错误，我尝试了很多修复但似乎没有解决这个问题。
这就是我的 modelsim 成绩单所说的：
**错误：（vsim-3389）C：/Users/VRN/Desktop/sha256/t_processing.v（31）：在连接的模块（第5个连接）中找不到端口'a_in'。
# 时间：0 ps 迭代：0 实例：/t_processing/uut 文件：C:/Users/VRN/Desktop/sha256/interative_processing.v
输入端口的 7 个类似错误
`timescale 1ns / 1ps
module interative_processing(clk,rst,w,k,counter_iteration,padding_done,a_out,b_out,c_out,d_out,e_out,f_out,g_out,h_out
);
input clk,rst,padding_done;
input [6:0] counter_iteration;
input [31:0] w,k;
output reg [31:0] a_out,b_out,c_out,d_out,e_out,f_out,g_out,h_out;
reg temp_case,temp_if;
reg [31:0] a_temp,b_temp,c_temp,d_temp,e_temp,f_temp,g_temp,h_temp;
reg [31:0] semation_0,semation_1,ch,maj;
always@(posedge clk)
begin
if(rst==0)
begin
temp_case=1'b0;
a_out=32'h6a09e667;
b_out=32'hbb67ae85;
c_out=32'h3c6ef372;
d_out=32'ha54ff53a;
e_out=32'h510e527f;
f_out=32'h9b05688c;
g_out=32'h1f83d9ab;
h_out=32'h5be0cd19;
end
else
begin
semation_0=({a_out[1:0],a_out[31:2]}) ^ ({a_out[12:0],a_out[31:13]}) ^ ({a_out[21:0],a_out[31:22]}); //last 22 ROTR22
semation_1=({e_out[5:0],e_out[31:6]}) ^ ({e_out[10:0],e_out[31:11]}) ^ ({e_out[24:0],e_out[31:25]});
maj=(a_out & b_out) ^ (a_out & c_out) ^ (b_out & c_out);
ch=(e_out & f_out) ^ (~e_out & g_out);
if(counter_iteration==65)
begin
a_out=a_out;
b_out=b_out;
c_out=c_out;
d_out=d_out;
e_out=e_out;
f_out=f_out;
g_out=g_out;
h_out=h_out;
end
else
begin
if(padding_done==1)
begin
case(temp_case)
1'b0: temp_case=1'b1;
1'b1: temp_if=1'b1;
endcase
end
if(temp_if==1 && counter_iteration!=64)
begin
a_temp= h_out + semation_1 + ch + k + w + semation_0 + maj; // T2= semation_0 + maj(a,b,c);
b_temp= a_out;
c_temp= b_out;
d_temp= c_out;
e_temp= d_out + h_out + semation_1 + ch + k + w; //T1 = h_out + semation_1 + ch + k + w;
f_temp= e_out;
g_temp= f_out;
h_temp= g_out;
a_out=a_temp;
b_out=b_temp;
c_out=c_temp;
d_out=d_temp; //alternative of non-blocking though
e_out=e_temp;
f_out=f_temp;
g_out=g_temp;
h_out=h_temp;
end
end
end
end
endmodule
和我的测试台：
`timescale 1ns / 1ps
module t_processing;
// Inputs
reg clk;
reg rst;
reg [31:0] w;
reg [31:0] k;
reg [31:0] a_in;
reg [31:0] b_in;
reg [31:0] c_in;
reg [31:0] d_in;
reg [31:0] e_in;
reg [31:0] f_in;
reg [31:0] g_in;
reg [31:0] h_in;
// Outputs
wire [31:0] a_out;
wire [31:0] b_out;
wire [31:0] c_out;
wire [31:0] d_out;
wire [31:0] e_out;
wire [31:0] f_out;
wire [31:0] g_out;
wire [31:0] h_out;
// Instantiate the Unit Under Test (UUT)
interative_processing uut (
.clk(clk),
.rst(rst),
.w(w),
.k(k),
.a_in(a_in),
.b_in(b_in),
.c_in(c_in),
.d_in(d_in),
.e_in(e_in),
.f_in(f_in),
.g_in(g_in),
.h_in(h_in),
.a_out(a_out),
.b_out(b_out),
.c_out(c_out),
.d_out(d_out),
.e_out(e_out),
.f_out(f_out),
.g_out(g_out),
.h_out(h_out)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
w = 0;
k = 0;
a_in = 0;
b_in = 0;
c_in = 0;
d_in = 0;
e_in = 0;
f_in = 0;
g_in = 0;
h_in = 0;
end
initial
begin // Wait 100 ns for global reset to finish
#100;
end
initial clk=1'b0;
always @(clk) clk<= #5 ~clk;
initial
begin
rst = 1'b0;
#10 rst = 1'b1;
k = 32'hc67178f2;
w = 32'h12b1edeb;
a_in = 32'hd39a2165;
c_in = 32'hb85e2ce9;
d_in = 32'hb6ae8fff;
e_in = 32'hfb121210;
f_in = 32'h948d25b6;
g_in = 32'h961f4894;
h_in = 32'hb21bad3d;
b_in= 32'h04d24d6c;
end
endmodule