此代码在检测到上升沿时生成 8 个时钟周期的 HIGH 输出enable
(因为它似乎是问题所要求的)。
从您的问题描述、逻辑和尝试中可以清楚地看出,您不需要count
作为输入(您无法初始化输入,因为它们是从模块外部触发的)。正如@Mortada 所说,你不应该把enable
总是块的灵敏度列表,最好在总是块enable
内检测信号的正边缘。平均值的正边缘enable
=> 之前的值enable
是 0,现在是 1。此外,您应该使用初始块来初始化您的寄存器。所以下面的代码应该没问题:
module clkgenerator(
input clk,
input enable,
output reg andpulse
);
reg [3:0] count;
reg previous_enable; //stores previous value of enable (1 clock earlier)
reg pulse_enable; //enables the pulse if positive edge of enable is detected
initial // this block is used to initialize the registers
begin
count <= 4'b0000;
andpulse <= 1'b0;
pulse_enable <= 1'b0;
previous_enable <= 1'b0;
end
always@(posedge clk)
begin
if(enable > previous_enable) //if enable > previous_enable it means positive edge was detected
pulse_enable <= 1'b1; //makes if condition that generates the pulse True for 8 clock cycles
if(pulse_enable)
begin
andpulse <= 1;
if(count == 4'b1000)
begin
andpulse <= 0;
count <= 4'b0;
pulse_enable <= 1'b0;
end
else
count <= count + 1;
end
else
count <= 1'b0;
previous_enable <= enable; //to be used in next stage
end //end of always block
endmodule
//This code is error free