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定义：

       `define AIF_MSB(AIF_i) (AIF_i == 0)?0 :\
                       (AIF_i == 1)?1 :\
                       (AIF_i == 2)?2 :\
                       (AIF_i == 3)?3 :\
                       (AIF_i == 4)?4 :\
                       (AIF_i == 5)?5 :\
                       (AIF_i == 6)?6 :\
                       (AIF_i == 7)?7 :\
                       (AIF_i == 8)?8 :\
                       (AIF_i == 9)?9 :\
                       (AIF_i == 10)?10 :\
                       (AIF_i == 11)?11 :\
                       (AIF_i == 12)?12 :\
                       (AIF_i == 13)?13 :\
                       (AIF_i == 14)?14 :\
                       (AIF_i == 15)?15 :\
                       (AIF_i == 16)?16 :\
                       (AIF_i == 17)?17 :\
                       (AIF_i == 18)?18 :\
                       (AIF_i == 19)?19 :0

    genvar AIF_i;
    generate
    for(AIF_i = 0; AIF_i < 16; AIF_i++)
    begin

CHECKER_71 :   assert 
    property(p_GGIS_invalid_chk(GGIS_ADDR,`AIF_MSB(AIF_i),`AIF_LSB(AIF_i),dut_if.lo_GGIS_AIF[AIF_i],
             event_if.fab_rd_res_txed, INTR_WR_REQ, AIF_i))else
              begin
               `uvm_error(log,$psprintf("CHECKER_71 :GGIS.AIF[%0d] is failed for 68 | 69 | 70",AIF_i));
             end

end
endgenerate

property p_GGIS_invalid_chk(addr,msb,lsb,field, req_type, pkt_type,AIF_i);
@(posedge clk_apb)
  $changed(field)
  |-> ((seq_reset_chk_RC(field,0,10).triggered)                                                                             
or
       (seq_GGIS_wr_set_trig_RC(addr,msb,lsb,field).triggered)                                               
or
       (seq_GGIS_set_chk_RC(addr,msb,lsb,req_type, pkt_type, 
field,AIF_i).triggered));
endproperty

sequence seq_reset_chk_RC(field,lower,upper);
 @(posedge clk_apb)
   (seq_reset_trig_FC.triggered
    ##[lower:upper] (seq_clr_chk_FC(field)));
endsequence

sequence seq_GGIS_wr_set_trig_RC(addr,msb,lsb,field);
  @(posedge clk_apb)
  (seq_GGIS_wr_set_trig_FC(addr,msb,lsb,field).triggered)
  ##[0:10] (field == 0);
endsequence

sequence seq_GGIS_AIF17_set_RC(addr,msb,lsb,field);
@(posedge clk_apb)
    (seq_GGIS_AIF17_trig_FC.triggered)
    ##[0:10] ((seq_wr_set_chk_FC(field))                                                                           
or
              (seq_reset_trig_FC.triggered)                                         
or
              (seq_GGIS_wr_set_trig_FC(addr,msb,lsb,field).triggered));
Endsequence

sequence seq_wr_set_chk_FC(field);
 @(posedge clk_apb)
   (field == 1'b1);
endsequence

sequence seq_reset_trig_FC;
 @(posedge clk_apb)
   ($changed(dut_if.lo_GSWR_GR)         &&
   (dut_if.lo_GSWR_GR == 1'b1));
endsequence


sequence seq_GGIS_wr_set_trig_FC(addr,msb,lsb,field);
 @(posedge clk_apb)
  (seq_is_field_write(addr, msb, lsb)     and
  (apb_master_if.pwdata[msb:lsb] == 1)    and
  (seq_wr_set_chk_FC(field)));
endsequence
  1. 代码按上述格式编写。（使用的属性和序列定义如下）
  2. 定义语句用于不同的 AIF 值（可能是 0 到 50）
  3. 每当调用它时，都会评估并获取 AIF 值我想减少在生成块中使用此操作所花费的时间。
  4. 目前我面临性能问题。
  5. 我想知道编写上述代码的另一种方法，这将减少编译和模拟的时间
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