我正在尝试将廉价的 FPGA（ep2c5t144 Altera Cyclone II 迷你板）与 SNES 连接，以充当 SNES 控制器。到目前为止，它似乎可以打开和关闭......当前的问题是，它在打开后工作了大约 1 秒钟......但随后似乎陷入了一种状态，直到它被重置。
由于我花了很长时间查看逻辑问题的代码，我开始怀疑使用 FPGA 是否是一些奇怪的怪癖，但我已经尝试过测试任何未定义的状态，而且还没有没有解决问题。我将在下面发布 SNES 代码，以及显示问题的廉价逻辑分析仪的输出。警告，代码非常混乱......特别是我改变了一些东西来尝试修复它。任何想法都非常感谢！
非常感谢您的帮助！
逻辑分析仪的问题：
当请求失败时 - 似乎错误地直接转换到“工作”状态并由于某种原因卡住
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity snes_controller is
generic (
hp : integer := 300
);
port (
clk : in std_logic;
latch : in std_logic;
data : out std_logic := '0';
clock : in std_logic;
enable : in std_logic;
btn_B : in std_logic;
btn_Y : in std_logic;
btn_select : in std_logic;
btn_start : in std_logic;
btn_up : in std_logic;
btn_down : in std_logic;
btn_left : in std_logic;
btn_right : in std_logic;
btn_A : in std_logic;
btn_X : in std_logic;
btn_L : in std_logic;
btn_R : in std_logic;
helpA : out std_logic := '0';
helpB : out std_logic := '0';
helpC : out std_logic := '0';
helpD : out std_logic := '0';
helpE : out std_logic := '0'
);
end entity;
architecture Behav of snes_controller is
signal buttons : unsigned(16 downto 0) := "10000000000000000";
type state_type is (s_idle, s_latching_1, s_latching_2, s_working);
signal state : state_type := s_idle;
type cycle_type is (c_high, c_low);
signal cycle : cycle_type := c_high;
begin
process (clk)
variable i : integer range 0 to 16;
variable count : integer range 0 to hp;
begin
if(rising_edge(clk)) then
data <= not buttons(i);
if(state = s_latching_1 or state = s_latching_2 or state = s_working) then
if(count < hp) then
count := count+1;
else
count := 0;
if(state = s_latching_1) then
if(latch = '1') then
state <= s_latching_2;
buttons(0) <= btn_B;
buttons(1) <= btn_Y;
buttons(2) <= btn_select;
buttons(3) <= btn_start;
buttons(4) <= btn_up;
buttons(5) <= btn_down;
buttons(6) <= btn_left;
buttons(7) <= btn_right;
buttons(8) <= btn_A;
buttons(9) <= btn_X;
buttons(10) <= btn_L;
buttons(11) <= btn_R;
else
state <= s_idle;
end if;
elsif(state = s_latching_2) then
state <= s_working;
i := 0;
cycle <= c_high;
elsif(state = s_working) then
if(latch = '1') then
state <= s_idle;
helpD <= '1';
elsif(cycle = c_low) then
cycle <= c_high;
if(i < 16) then
i := i+1;
else
state <= s_idle;
helpD <= '0';
helpE <= '0';
end if;
else
cycle <= c_low;
end if;
end if;
end if;
elsif(state = s_idle) then
if(latch = '1') then
state <= s_latching_1;
count := 0;
i := 0;
end if;
else
helpE <= '1';
state <= s_idle;
count := 0;
i := 0;
end if;
end if;
end process;
process(state)
begin
if(state = s_idle) then
helpA <= '0';
helpB <= '0';
elsif(state = s_latching_1) then
helpA <= '1';
helpB <= '0';
elsif(state = s_latching_2) then
helpA <= '0';
helpB <= '1';
elsif(state = s_working) then
helpA <= '1';
helpB <= '1';
else
helpA <= clk;
helpB <= not clk;
end if;
if(cycle = c_low) then
helpC <= '0';
elsif(cycle = c_high) then
helpC <= '1';
end if;
end process;
end Behav;