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我有以下代码将无符号的低位转换为关联列表中的 std_logic_vector 。我可以使用 GHDL 编译它并运行仿真。但是输出波形中有一些未知（'U'）位，inner_counter尽管没有未知位counter。（波形图像遵循代码。）我认为 和 的位inner_counter应该counter具有保存值。有谁知道这是 GHDL 的预期行为或错误？

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_bench is
end test_bench;

architecture default of test_bench is
  signal clk : std_logic := '0';
  signal counter : unsigned(7 downto 0) := (others => '0');

  component inner
    port (
    clk : in std_logic;
    inner_counter : in std_logic_vector(6 downto 0));
  end component;

begin

  i0 : inner port map (
  clk => clk,
  inner_counter => std_logic_vector(counter(6 downto 0)));

  process
  begin
    clk <= '1';
    wait for 1 ns;
    clk <= '0';
    wait for 1 ns;
  end process;

  process(clk)
  begin
    if rising_edge(clk) then
      counter <= counter + 1;
    end if;
  end process;

end default;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity inner is
  port (
  clk : in std_logic;
 inner_counter : in std_logic_vector(6 downto 0));
end inner;

architecture default of inner is
begin
  --do something
end architecture;

的波形图像counter和inner_counter

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