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我正在为我的教育学习模型检查和 NuSMV。我可以编辑和运行 NuSMV 代码，并且我对 UART 是什么以及做什么有相当了解。

我的任务是用 NuSMV 对 UART 进行正式建模，但目前我不知道该怎么做。我知道 UART 将一个字节作为八个连续位传输，但我该如何建模呢？

我有一个互斥代码作为起点：

>NuSMV.exe mutex.smv
*** This is NuSMV 2.6.0 (compiled on Wed Oct 14 15:37:51 2015)
*** Enabled addons are: compass
*** For more information on NuSMV see <http://nusmv.fbk.eu>
*** or email to <nusmv-users@list.fbk.eu>.
*** Please report bugs to <Please report bugs to <nusmv-users@fbk.eu>>

*** Copyright (c) 2010-2014, Fondazione Bruno Kessler

*** This version of NuSMV is linked to the CUDD library version 2.4.1
*** Copyright (c) 1995-2004, Regents of the University of Colorado

*** This version of NuSMV is linked to the MiniSat SAT solver.
*** See http://minisat.se/MiniSat.html
*** Copyright (c) 2003-2006, Niklas Een, Niklas Sorensson
*** Copyright (c) 2007-2010, Niklas Sorensson

-- specification EF (state1 = c1 & state2 = c2)  is false
-- as demonstrated by the following execution sequence
Trace Description: CTL Counterexample
Trace Type: Counterexample
  -> State: 1.1 <-
    state1 = n1
    state2 = n2
    turn = 1
-- specification AG (state1 = t1 -> AF state1 = c1)  is true
-- specification AG (state2 = t2 -> AF state2 = c2)  is true

编码

MODULE main


VAR

state1: {n1, t1, c1};

ASSIGN

init(state1) := n1;

next(state1) := 
case
   (state1 = n1) & (state2 = t2): t1;
   (state1 = n1) & (state2 = n2): t1;
   (state1 = n1) & (state2 = c2): t1;
   (state1 = t1) & (state2 = n2): c1;
   (state1 = t1) & (state2 = t2) & (turn = 1):  c1;
   (state1 = c1): n1;
   TRUE : state1;
esac;




VAR

state2: {n2, t2, c2};

ASSIGN

init(state2) := n2;

next(state2) := 
case
   (state2 = n2) & (state1 = t1): t2;
   (state2 = n2) & (state1 = n1): t2;
   (state2 = n2) & (state1 = c1): t2;
   (state2 = t2) & (state1 = n1): c2;
   (state2 = t2) & (state1 = t1) & (turn = 2):  c2;
   (state2 = c2): n2;
   TRUE : state2;
esac;


VAR

turn: {1, 2};

ASSIGN

init(turn) := 1;

next(turn) := 
case
   (state1 = n1) & (state2 = t2): 2;
   (state2 = n2) & (state1 = t1): 1;
   TRUE : turn;
esac;

SPEC

EF((state1 = c1) & (state2 = c2))

SPEC

AG((state1 = t1) -> AF (state1 = c1))

SPEC

AG((state2 = t2) -> AF (state2 = c2))
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1 回答 1

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在进入 smv 模型之前，您需要了解对 UART 组件建模感兴趣的详细程度。首先以不同的形式对组件进行建模会很有帮助，这样您就不会陷入语法问题。组件的输入是什么？输出是什么？有内部状态吗？内部状态如何随时间变化，尤其是一步变化？

如果您熟悉硬件描述语言（例如，Verilog 和 VHDL），这将是一个很好的起点，因为 SMV 中的转换可以看作是时钟滴答。如果你不懂这些语言，你可以试着写一个软件来代替；这将帮助您了解系统的输入/输出，但转换为 SMV 不会那么直接。

对于非常有状态的组件，手动绘制相应的自动机可能会有所帮助。

于 2017-02-26T17:00:52.623 回答