我很难理解这段代码的效果:我的组件:
library IEEE;
use IEEE.std_logic_1164.all;
entity problem is
port(
clk : in std_logic;
a : in std_logic);
end problem;
architecture impl of problem is
signal a_sig : std_logic;
begin
clk_proc : process(clk)
begin
if rising_edge(clk) then
a_sig <= '0';
end if;
end process;
a_proc : process(a)
begin
report "a received : " & std_logic'image(a);
a_sig <= a;
end process;
a_sig_proc : process(a_sig)
begin
report "a_sig set : " & std_logic'image(a_sig);
end process;
end impl;
这是我的 testbench.vhd:
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component problem is
port ( clk : in std_logic;
a : in std_logic);
end component;
constant clk_period : time := 1 ms;
signal clk_sig : std_logic;
signal a_sig : std_logic;
begin
dut : problem port map (clk_sig, a_sig);
process
begin
clk_sig <= '1';
wait for clk_period/2;
clk_sig <= '0';
wait for clk_period/2;
end process;
process
begin
wait for clk_period * 0.75;
a_sig <= '1';
end process;
end tb;
运行代码的结果如下:
$ ghdl -r testbench --vcd=testbench.vcd --stop-time=2ms
problem.vhd:23:5:@0ms:(report note): a received : 'U'
problem.vhd:29:5:@0ms:(report note): a_sig set : 'U'
problem.vhd:23:5:@750us:(report note): a received : '1'
problem.vhd:29:5:@1ms:(report note): a_sig set : 'X'
./testbench:info: simulation stopped by --stop-time
我可以理解在 0 毫秒接收到的“U”信号,并且可以理解在 750 微秒时在 issue.a_proc 中接收到的“1”信号。让我困惑的第一件事是,为什么在同一进程中设置 a_sig 不会触发 issue.a_sig_proc ?然后,当 issue.a_sig_proc 被触发时,a_sig 的值为“X”。如果有人能指出我的资源来解释这一点,那就太好了:)
提前致谢!