我正在尝试在 ghdl 中使用我自己的包。有人可以帮我解决结构和编译问题。目前我的代码如下所示:
在 ./my_package/my_package.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package my_package is
constant my_constant : std_logic_vector(3 downto 0) := "1111";
end my_package;
我在 my_package 中编译它,如下所示:
myname@myrechner my_package$ ghdl -a --work=my_package my_package.vhd
然后在 ./uses_my_package/uses_my_package.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity uses_my_package is
port(
vector_in : in std_logic_vector(3 downto 0);
vector_out : out std_logic_vector(3 downto 0));
end uses_my_package;
architecture impl of uses_my_package is
begin
vector_out <= vector_in;
end impl;
在 ./uses_my_package/testbench.vhd 中:
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.my_package.all;
entity testbench is
end testbench;
architecture tb of testbench is
component uses_my_package is
port (
vector_in : in std_logic_vector(3 downto 0);
vector_out : out std_logic_vector(3 downto 0));
end component;
signal vector_in_signal : std_logic_vector(3 downto 0);
signal vector_out_signal : std_logic_vector(3 downto 0);
constant clk_period : time := 1 ms;
begin
dut : uses_my_package
port map (vector_in_signal, vector_out_signal);
process
begin
vector_in_signal <= "0000";
wait for clk_period;
assert vector_out_signal = my_constant report "fail 0000" severity error;
vector_in_signal <= "1111";
wait for clk_period;
assert vector_out_signal = my_constant report "fail 1111" severity error;
wait;
end process;
end tb;
谁能告诉我应该如何编译这个程序或指向我关于 ghdl 中的包和库的教程?我的 google-foo 目前似乎很虚弱。谢谢!