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我正在尝试模拟 VHDL 项目，但 modelsim 给了我以下错误消息：

Error: (vsim-3173) Entity 'C:/Users/chose/Documents/CTD/teste/SELETORES/simulation/modelsim/rtl_work.seletores' has no architecture.

我尝试创建另一个项目，它给了我同样的错误。我之前能够模拟其他项目，做同样的事情。

我正在运行 Quartus Prime Lite Edition 16.0 和 Modelsim 10.5b。我试图模拟的代码是：

library IEEE;
use IEEE.Std_Logic_1164.all;

entity SELETORES is
port(   IN_POT: in std_logic;
        OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW
                :   in  std_logic_vector(9 downto 0);
        MODE    :   in  std_logic_vector(39 downto 0);
        SEL_DISP, SEL_LED
                :   in      std_logic_vector(1 downto 0);
        LED_OUT, SEL_TIME, SEL_POT
                :   out std_logic_vector(9 downto 0);
        REG :   out std_logic_vector(19 downto 0)
        );
end SELETORES;

architecture SELETORES_bhv of SELETORES is
    signal decod_mux : std_logic_vector(19 downto 0);

component mux_4x1_20
port (W,X,Y,Z: in std_logic_vector(19 downto 0);
        S: in std_logic_vector(1 downto 0);
        F: out std_logic_vector(19 downto 0)
      );
end component;

component mux_4x1_10
port (W,X,Y,Z: in std_logic_vector(9 downto 0);
        S: in std_logic_vector(1 downto 0);
        F: out std_logic_vector(9 downto 0)
      );
end component;

component mux_2x1
port (W,X: in std_logic_vector(9 downto 0);
        S: in std_logic;
        F: out std_logic_vector(9 downto 0)
      );
end component;

component decod_time
port(   ENTRADA : in    std_logic_vector(9 downto 0);
        SAIDA: out  std_logic_vector(19 downto 0)
        );
end component;

begin

L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT);

L2 : mux_2x1 port map (SW, MODE(19 downto 10), SEL_DISP(0) and not(SEL_DISP(1)), SEL_TIME);

L3 : decod_time port map (CONTA, decod_mux);

L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG);

L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT);

end SELETORES_bhv;
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1 回答 1

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首先，您的 L2 组件实例化中有一些语法错误。其次，在我看来，这是正确的做法（港口地图中不允许运营商）：

library IEEE;
use IEEE.std_logic_1164.all;

entity SELETORES is
port(   IN_POT: in std_logic;
        OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW
                :   in  std_logic_vector(9 downto 0);
        MODE    :   in  std_logic_vector(39 downto 0);
        SEL_DISP, SEL_LED
                :   in      std_logic_vector(1 downto 0);
        LED_OUT, SEL_TIME, SEL_POT
                :   out std_logic_vector(9 downto 0);
        REG :   out std_logic_vector(19 downto 0)
        );
end SELETORES;

architecture SELETORES_bhv of SELETORES is

-- Component declarations

component mux_4x1_20
  port (W,X,Y,Z: in std_logic_vector(19 downto 0);
        S1: in std_logic_vector(1 downto 0);
        F: out std_logic_vector(19 downto 0)
        );
end component;

component mux_4x1_10
  port (W,X,Y,Z: in std_logic_vector(9 downto 0);
        S2: in std_logic_vector(1 downto 0);
        F: out std_logic_vector(9 downto 0)
        );
end component;

component mux_2x1
  port (W,X: in std_logic_vector(9 downto 0);
        S3: in std_logic;
        F: out std_logic_vector(9 downto 0)
        );
end component;

component decod_time
  port(ENTRADA : in    std_logic_vector(9 downto 0);
       SAIDA: out  std_logic_vector(19 downto 0)
       );
end component;

--End component declarations

-- Internal signals

signal decod_mux : std_logic_vector(19 downto 0);
signal foobar: std_logic;

--End Internal Signals

begin

foobar <= SEL_DISP(0) AND NOT SEL_DISP(1);

L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT);

L2 : mux_2x1 port map (SW, MODE(19 downto 10), foobar, SEL_TIME);

L3 : decod_time port map (CONTA, decod_mux);

L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG);

L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT);

end SELETORES_bhv;

我已经在 ModelSim 10.1c 上进行了测试，没有任何问题。

于 2016-11-28T01:13:01.593 回答