我正在尝试通过使用 for 循环使用波纹进位加法器来执行加法,并且我希望该操作仅在时钟的位置执行。为此,我使用了一个生成块并在生成块内使用了 for 循环。如果我不使用 always 语句,它会正常工作,但是当我添加 always 块时,它会在模拟时导致错误。下面是代码:
genvar i;
generate
always @(posedge clk)
for(i=0;i<=31;i=i+1) begin : generate_block
fulladd f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));
end
end
endgenerate
这里 fulladd 是一个不同的模块。
以下是我在模拟时遇到的错误:
Error-[IBLHS-CONST] Illegal behavioral left hand side
add32.v, 36
Constant Expression cannot be used on the left hand side of this assignment
The offending expression is : i
Source info: i = 0;
Error-[IBLHS-CONST] Illegal behavioral left hand side
add32.v, 36
Constant Expression cannot be used on the left hand side of this assignment
The offending expression is : i
Source info: i = (i + 1);
Error-[SE] Syntax error
Following verilog source has syntax error :
"add32.v", 37: token is '('
fulladd
f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));
add32.v 是设计模块名称。我用过概要 vcs。我是verilog编程的新手,请解释我错误的基本概念。提前致谢