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我在 VCS 合成器中收到此错误。我已经尝试了一切，但这对我来说没有意义。它说 VectorY[0]、VectorY[1]、VectorY[2]、VectorY[3] 或直接连接的网络，由多个源驱动，并且至少一个源是恒定网络。(ELAB-368)

module control (clk, start, S1S2mux, newDist, CompStart, PEready, VectorX, VectorY, addressR, addressS1, addressS2,completed);

    input clk;
    input start;
    output reg [15:0] S1S2mux;
    output reg [15:0] newDist;
    output CompStart;
    output reg [15:0] PEready;
    output reg [3:0] VectorX,VectorY;
    output reg [7:0] AddressR;
    output reg [9:0] AddressS1,AddressS2; 
    reg [12:0] count;
    output reg completed;
    integer i;

    assign CompStart = start;

    always @(posedge clk) begin
        if(start==0) begin 
            count<= 12'b0; 
            completed<=0; 
            newDist<=0;
            PEready<=0;
            VectorX<=0;
            VectorY<=0;
        end
        else if (completed==0) 
            count <= count+1'b1;
    end

    always @(count) begin
        for (i = 0; i < 15; i = i+1)
        begin 
            newDist [i] = (count [7:0] == i);
            PEready [i] = (newDist [i] && !(count < 8'd256));
            S1S2mux [i] = (count [3:0] > i);
        end
        addressR = count [7:0];
        addressS1 = (count[11:8] + count[7:4] >> 4)*5'd32 + count [3:0];
        addressS2 = (count[11:8] + count[7:4] >> 4)*4'd16 + count [3:0];
        VectorX = count[3:0] - 4'd7;
        VectorY = count[11:8] >> 4 - 4'd7;
        completed = (count == 4'd16 * (8'd256 + 1));
    end
endmodule
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1 回答 1

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您可能可以这样做...在systemverilog中

创建另一个逻辑变量

logic [3:0] VectorY_next;

然后在顺序块中，执行 ..

always_ff begin
        if(start==0) begin 
            count<= 12'b0; 
            completed<=0; 
            newDist<=0;
            PEready<=0;
            VectorX<=0;
            VectorY<=0;
        end
        else if (completed==0) begin 
            count <= count+1'b1;
            VectorY <= VectorY_next;
        end
end

在组合块中，您可以编写...

always_comb begin
        VectorY_next = VectorY;
        for (i = 0; i < 15; i = i+1)
        begin 
           .....
        VectorY_next = count[11:8] >> 4 - 4'd7;
        completed = (count == 4'd16 * (8'd256 + 1));
    end
endmodule

并且可能对其他端口也这样做。要使用 systemverilog 运行，只需在命令行中使用 -sv 选项。

于 2016-10-23T02:57:24.467 回答