我想测量信号的上升转换和下降转换的数量。我将信号用作时钟并实现了 2 个计数器。一个计数器在每个上升沿递增,另一个在每个下降沿递增。我将这两个计数器的结果相加以获得最终计数值。
有没有更好的方法来实现这个逻辑?什么是最稳健的方法?
module clock_edge_counter (
clock_edge_count, // Output of the counter ,
clk , // clock Input
stop ,
reset
);
parameter CNTR_WIDTH = 16;
input clk ;
input stop ;
input reset ;
output [CNTR_WIDTH:0] clock_edge_count;
wire [CNTR_WIDTH:0] clock_edge_count;
reg [CNTR_WIDTH-1:0] clock_negedge_edge_count;
reg [CNTR_WIDTH-1:0] clock_posedge_edge_count;
always @(posedge clk or posedge reset)
if (reset) begin
clock_posedge_edge_count <= 0;
end
else if (!stop) begin
clock_posedge_edge_count <= clock_posedge_edge_count + 1;
end
always @(negedge clk or posedge reset)
if (reset) begin
clock_negedge_edge_count <= 0;
end
else if (!stop) begin
clock_negedge_edge_count <= clock_negedge_edge_count + 1;
end
assign clock_edge_count = clock_negedge_edge_count + clock_posedge_edge_count;
endmodule