下面的代码是一个简单的 16 位加法器（它只使用一个四位加法器）。我试着避开所有的闩锁。但我无法删除图像中突出显示的锁存器（sum_16_temp）。谁能帮我避免这个闩锁。如果有人能帮助我理解RTL_ROM的用途（在闩锁之前的next_state_i ），我将不胜感激
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sixteen_bit_adder is
Port ( a_16 : in STD_LOGIC_VECTOR (15 downto 0);
b_16 : in STD_LOGIC_VECTOR (15 downto 0);
carry_in_16 : in STD_LOGIC;
clk : in std_logic;
reset_16 : in std_logic;
done_addition : out std_logic;
sum_16 : out STD_LOGIC_VECTOR (15 downto 0);
carry_out_16 : out STD_LOGIC);
end sixteen_bit_adder;
architecture structural of sixteen_bit_adder is
------------------signal declaration------------------
signal sum_16_temp : STD_LOGIC_VECTOR (15 downto 0):=x"0000"; -- temporary register for sum
signal carry_out_temp : std_logic; -- temporary register for carry
type state_type is (s0,s1,s2,s3,s4); -- states;
signal next_state,state: state_type;
signal a_4,b_4,sum_4: STD_LOGIC_VECTOR (3 downto 0):=x"0"; -- temp for 4 bit component inputs
signal carry_in_4,carry_out_4,done_temp: std_logic:='0';
-------end of signal declaration-------
------component declaration-------------
component four_bit_adder is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
carry_in : in STD_LOGIC;
sum_4 : out STD_LOGIC_VECTOR (3 downto 0);
carry_out : out STD_LOGIC);
end component four_bit_adder;
------end of component declaraton--------
begin
four_bit_adder1: four_bit_adder port map(a_4, b_4, carry_in_4, sum_4, carry_out_4);
flopping_process: process(reset_16,clk)
begin
if reset_16 ='1' then
sum_16 <= x"0000";
carry_out_16 <= '0';
state <= s0;
done_addition <= '0';
elsif rising_edge(clk) then
sum_16 <= sum_16_temp;
carry_out_16 <= carry_out_temp;
state <= next_state;
done_addition <= done_temp;
end if;
end process;
State_machine: process(state,reset_16)
begin
if reset_16 ='0' then
case state is
when s0 =>
a_4 <= a_16(3 downto 0);
b_4 <= b_16(3 downto 0);
carry_in_4 <= carry_in_16;
next_state <= s1;
sum_16_temp(3 downto 0) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s1 =>
a_4 <= a_16(7 downto 4);
b_4 <= b_16(7 downto 4);
carry_in_4 <= carry_out_4;
sum_16_temp(3 downto 0) <= sum_4;
next_state <= s2;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s2 =>
a_4 <= a_16(11 downto 8);
b_4 <= b_16(11 downto 8);
carry_in_4 <= carry_out_4;
sum_16_temp(7 downto 4) <= sum_4;
next_state <= s3;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when s3 =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
sum_16_temp(11 downto 8) <= sum_4;
next_state <= s4;
carry_out_temp <= carry_out_4;
done_temp <= '0';
when others =>
a_4 <= a_16(15 downto 12);
b_4 <= b_16(15 downto 12);
carry_in_4 <= carry_out_4;
sum_16_temp(15 downto 12) <= sum_4;
carry_out_temp <= carry_out_4;
done_temp <= '1';
next_state <= s4;
end case;
else
a_4 <= x"0";
b_4 <= x"0";
carry_in_4 <= '0';
sum_16_temp <= x"0000";
carry_out_temp <= '0';
done_temp <= '0';
next_state <= s0;
end if;
end process;
end structural;
