我正在尝试将此代码实现到一个程序中，该程序将信号的脉冲宽度显示到 basys2 板上的七段显示器上，但是当我将代码下载到板上时，它只显示“0001”，我发现它只显示了 1执行“x<=a_count_pw+1”的部分。看起来它只是加了 1，即使没有输入信号也是如此。我也收到此警告“信号不完整。信号不驱动设计中的任何负载引脚。” 这应该是我的输入信号？这是我的代码。非常感谢您的任何帮助。
顶级模块：main_top - 行为（main_top.vhd）
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity main_top is
port(
J3_IO1 : in std_logic;
mclk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR(3 downto 0);
a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
an : out STD_LOGIC_VECTOR(3 downto 0);
dp : out STD_LOGIC
);
end main_top;
architecture Behaviral of main_top is
signal a_count_rst: STD_LOGIC;
signal a_count_pw: STD_LOGIC_VECTOR(15 downto 0);
signal a_count_pw_reported: STD_LOGIC_VECTOR(15 downto 0);
signal J3_IO1_q : STD_LOGIC;
signal J3_IO1_qq : STD_LOGIC;
component main
port(
x : in STD_LOGIC_VECTOR(15 downto 0);
clk : in STD_LOGIC;
clr : in STD_LOGIC;
a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
dp : out STD_LOGIC
);
end component;
signal x: STD_LOGIC_VECTOR (15 downto 0);
begin
process(mclk)
if mclk'event and mclk='1' then
-- Synchronous process, clock edge is outer "if"
if a_count_rst='1' then --synchronous reset
a_count_pw <= b"0000000000000000";
a_count_pw_reported <= a_count_pw_reported;
else
J3_IO1_q <= J3_IO1; -- First D FF stage
J3_IO1_qq <= J3_IO1_q; -- Second D FF stage for edge detect
if J3_IO1_qq = '0' and J3_IO1_q = '1' then -- Detect rising edge
a_count_pw <= b"0000000000000000"; -- Start from 0 at rising edge
elsif J3_IO1_qq = '1' and J3_IO1_q = '0' then -- Detect falling edge
a_count_pw_reported <= a_count_pw; -- Capture count
else
x <= a_count_pw + 1;
end if;
end if;
end if;
end process;
X1 : main port map
(x=>x, clk=>mclk, clr=>btn(3), a_to_g=>a_to_g, an=>an, dp=>dp);
end Behaviral;
这是用于多路复用显示的下一个模块。
模块：X1 - 主要 - 行为 (main.vhd)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity main is
port(
x : in STD_LOGIC_VECTOR(15 downto 0);
clk : in STD_LOGIC;
clr : in STD_LOGIC;
a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
dp : out STD_LOGIC;
btn : in STD_LOGIC_VECTOR(3 downto 0);
J3_IO1 : in STD_LOGIC;
a_count_pw : in STD_LOGIC_VECTOR(15 downto 0)
);
end main;
architecture Behaviral of main is
signal s : STD_LOGIC_VECTOR (1 downto 0);
signal aen : STD_LOGIC_VECTOR (3 downto 0);
signal clkdiv : STD_LOGIC_VECTOR (20 downto 0);
signal digit : STD_LOGIC_VECTOR (3 downto 0);
begin
s <= clkdiv(18 downto 17);
aen <= "1111";
dp <= '1';
--4 to 1 multiplex
process(s, x)
begin
case s is
when "00" => digit <= x(3 downto 0);
when "01" => digit <= x(7 downto 4);
when "10" => digit <= x(11 downto 8);
when others => digit <= x(15 downto 12);
end case;
end process;
process(digit)
begin
case digit is
when X"0" => a_to_g <= "1000000"; --0
when X"1" => a_to_g <= "1111001"; --1
when X"2" => a_to_g <= "0100100"; --2
when X"3" => a_to_g <= "0110000"; --3
when X"4" => a_to_g <= "0011001"; --4
when X"5" => a_to_g <= "0010010"; --5
when X"6" => a_to_g <= "0000010"; --6
when X"7" => a_to_g <= "1011000"; --7
when X"8" => a_to_g <= "0000000"; --8
when X"9" => a_to_g <= "0010000"; --9
when X"A" => a_to_g <= "0001000"; --A
when X"B" => a_to_g <= "0000011"; --b
when X"C" => a_to_g <= "1000110"; --C
when X"D" => a_to_g <= "0100001"; --d
when X"E" => a_to_g <= "0000110"; --E
when others => a_to_g <= "0001110"; --F
end case;
end process;
--digit control
process(s, aen)
begin
an <= "1111";
if aen(conv_integer(s)) = '1' then
an(conv_integer(s)) <= '0';
end if;
end process;
--clock divider
process(clk, clr)
begin
if clr ='1' then
clkdiv <= (others => '0');
elsif clk'event and clk = '1' then
clkdiv <= clkdiv +1;
end if;
end process;
end Behaviral;
这是我的 ucf 文件 ports.ucf
NET "mclk" LOC = "B8";
NET "a_to_g<0>" LOC = "L14";
NET "a_to_g<1>" LOC = "H12";
NET "a_to_g<2>" LOC = "N14";
NET "a_to_g<3>" LOC = "N11";
NET "a_to_g<4>" LOC = "P12";
NET "a_to_g<5>" LOC = "L13";
NET "a_to_g<6>" LOC = "M12";
NET "dp" LOC = "N13";
NET "an<3>" LOC = "K14";
NET "an<2>" LOC = "M13";
NET "an<1>" LOC = "J12";
NET "an<0>" LOC = "F12";
NET "btn<3>" LOC = "A7";
NET "J3_IO1" LOC = "J3";