vhdl - 使用 FPGA 的伺服控制 (Altera DE2)

Question

我正在创建一个 VHDL 代码，用于使用 DE2 开发套件上的 8 个开关控制伺服位置。代码完成后，我用伺服电机测试了代码，但它不起作用。然后我用时序分析做了一个波形仿真，发现波形有一些毛刺。这是故障的原因吗？如果是，我该如何解决这个问题？

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity servo_pwm is
PORT (
    clk50 : IN STD_LOGIC;
    clk   : IN  STD_LOGIC;
    reset : IN  STD_LOGIC;
    position   : IN  STD_LOGIC_VECTOR(7 downto 0);
    servo : OUT STD_LOGIC
);
end servo_pwm;

architecture Behavioral of servo_pwm is
signal cnt : unsigned(11 downto 0);
signal pwmi: unsigned(7 downto 0);
begin
pwmi <= unsigned(position);
start: process (reset, clk) begin
    if (reset = '1') then
        cnt <= (others => '0');
    elsif rising_edge(clk) then
        if (cnt = 2559) then    
            cnt <= (others => '0');
        else
            cnt <= cnt + 1;
        end if;
    end if;
end process;
servo <= '1' when (cnt < pwmi) else '0';
end Behavioral;

时钟分频器：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clk64kHz is
Port (
    clk    : in  STD_LOGIC;
    reset  : in  STD_LOGIC;
    clk_out: out STD_LOGIC
);
end clk64kHz;

architecture Behavioral of clk64kHz is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 195 := 0; --position 8bit
begin
freq_divider: process (reset, clk) begin
    if (reset = '1') then
        temporal <= '0';
        counter  <= 0;
      --elsif rising_edge(clk) then
        elsif (clk'event and clk = '1') then
        --if (counter = 390) then
        if (counter = 195) then
            temporal <= NOT(temporal);
            counter  <= 0;
        else
            counter <= counter + 1;
        end if;
    end if;
end process;

clk_out <= temporal;
end Behavioral;

矢量波形文件：