“无符号 8 位容错加法器”在“vhdl 代码”中添加两个 8 位数字。我已经尝试过下面的代码。它给出了这些错误 ** 错误:C:/Modeltech_pe_edu_10.4a/examples/etl1.vhd(34):靠近“信号”:语法错误 ** 错误:C:/Modeltech_pe_edu_10.4a/示例/etl1.vhd(41):“EOF”附近:语法错误
#下面的代码
enter code here
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity adr is
port (a,b: in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0));
end adr ;
architecture eta of adr is
signal hn,ln: std_logic_vector(7 downto 0);
signal parta2,partb2,hno:std_logic_vector(3 downto 0);
signal parta1,partb1: std_logic_vector(3 downto 0);
signal lno:std_logic_vector(3 downto 0);
begin
process (a,b)
begin
parta1<= a(7 downto 4); -- parta1<= a(7 downto 4);
parta2<= a(3 downto 0); --parta2<= a(3 downto 0);
partb1<= b(7 downto 4); --partb1<= b(7 downto 4);
partb2<= b(3 downto 0); -- partb2<= b(3 downto 0);
hno<= std_logic_vector(unsigned(parta1)+ unsigned(partb1)); --4 bit msb
lno<= std_logic_vector((unsigned(partb2))xor(unsigned(partb2)));--4bit lsb
Signal hn: std_logic_vector(7 downto 0) := hno(3 downto 0) & B"0000";-- concatenation of hn with zeros
Signal ln: std_logic_vector(7 downto 0) := B"0000" & lno(3 downto 0);--concatenation ln with zeros
output<=(hn or ln);
end process ;
。提前致谢..