我有一个带有层次结构的节奏示意图。我能够在命令行以批处理模式运行 si 网表以生成分层的 verilog 网表。我想知道是否有人知道是否有可能产生一个平面的verilog网表。我尝试了各种选择，但似乎无法让它发挥作用。谷歌上的搜索似乎对这是否可能给出了不同的意见。
我用于分层运行的 si.env 文件如下：
simLibName = "myLib"
simCellName = "myCell"
simViewName = "schematic"
simSimulator = "verilog"
simNotIncremental = 't
simReNetlistAll = 't
simViewList = '("gate" "functional" "verilog" "schematic" "symbol")
simStopList = '("functional" "verilog" "symbol")
simNetlistHier = t
simVerilogLaiLmsiNetlisting = 'nil
verilogSimViewList = '("gate" "functional" "verilog" "schematic" "symbol")
simVerilogAutoNetlisting = 't
simVerilogTestFixtureFlag = 'nil
simVerilogTestFixtureTemplate = "All"
simVerilogNetlistExplicit = 't
hnlVerilogTermSyncUp = 'nil
simVerilogFlattenBuses = 'nil
vtoolsUseUpperCaseFlag = 'nil
hnlVerilogCreatePM = 'nil
simVerilogTopLevelModuleName = ""
simHierarchyPrefix = ""
simNCVerilogHierPrefix = ""
verilogSimStopList = '("functional" "verilog" "symbol")
simVerilogPwrNetList = '("vddin_sub!" "vddout_sub!" "vddin!" "vddout!" "vddin_sub" "vddout_sub" "vddin" "vddout" "vddfx")
simVerilogGndNetList = '("vssfx!" "vss_sub!" "vssfx" "vss_sub")
vtoolsifForceReNetlisting = 'nil
simVerilogLibNames = '("stdcell_lib")
vlogifInternalTestFixtureFlag = 'nil
simVerilogBusJustificationStr = "U"
simVerilogTestFixtureTemplate = "All"
simVerilogDropPortRange = 't
simVerilogHandleUseLib = 'nil
simVerilogHandleAliasPort = 't
simVerilogPrintStimulusNameMappingTable = 'nil
simVerilogProcessNullPorts = 'nil
simVerilogIncrementalNetlistConfigList = 'nil
hnlVerilogNetlistStopCellImplicit = 'nil
simVerilogOverWriteSchTimeScale = 'nil
vlogifCompatibilityMode = "4.0"
simVerilogHandleSwitchRCData = 'nil
vlogifUseAssignsForAlias = 'nil
vlogifDeclareGlobalNetLocal = 'nil
vlogifSkipTimingInfo = 'nil
simVerilogEnableEscapeNameMapping = 't
simVerilogStopAfterCompilation = 't
simVerilogVhdlImport = 'nil
simVerilogTopCellCounter = 0
hnlSupportIterInst = 'nil
老实说，我不知道其中许多选项的作用。我可能已经定义了我不需要的东西。我真的只是想把它列入网表......不需要任何模拟设置。
谷歌搜索显示我需要在某些地方设置 fnl* 而不是 hnl*，但对于让这个平面网表正常工作的方法并没有真正具体说明。
想知道是否有人有这方面的经验并且能够使平面verilog网表正常工作。
谢谢！