verilog - Shift a number left in verilog and only retain upper bits

Question

I have the following wires in verilog:

wire [15:0] mywire;
wire [7:0] mywire_shifted
wire [4:0] shiftamount;

I want to shift mywire left by some amount, but only retain the upper 8 bits:

assign mywire_shifted = (mywire << shiftamount) >> 8;

Is there a cleaner way to do this?

Perhaps something like this:

assign {mywire_shifted,8'0} = mywire << shiftamount;

Answer 1

我认为您的第一个解决方案是干净的。但你也可以这样做

assign mywire_shifted = mywire[shiftamount+8 +: 8];

这表示从 LSB（shiftamount+8）开始返回下一个 MSB（高）8 位。