vhdl - 使用 Modelsim (VHDL) 模拟 INOUT 端口

Question

我试图用 Altera 的 Quartus 和 Modelsim 模拟 RAM 存储器。问题是，当我在测试台中为 data_inout 赋值并进行模拟时，波形始终处于“U”状态。当我执行 data_inout <= "0000000000001010"; 例如，或者如果我使用 data_inout <= aux_data; 我想要的只是测试它是否在数组上写入一些值，然后读取它们以进行大学练习，没什么特别的。知道如何模拟它吗？

谢谢。

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram_program is

    port(
        dir : in std_logic_vector (7 downto 0);
        read_write,cs : in std_logic;
        data_inout : inout std_logic_vector (15 downto 0)
        );

end entity ram_program;

architecture code_ram_program of ram_program is 

type tipo_ram is array (255 downto 0) of std_logic_vector (15 downto 0);
signal ram : tipo_ram;

begin
MEM_RAM: process (cs,read_write,datos_in_out,dir)
begin

    if (cs = '1' and read_write = '1') then
        ram(to_integer(unsigned(dir))) <= data_inout;
    end if;

    if (cs = '1' and read_write = '0') then
        data_inout <= ram(to_integer(unsigned(dir)));
    end if;

end process MEM_RAM;

end architecture code_ram_program;