verilog - 连接的向量在合成中被截断

Question

在尝试为线性函数移位寄存器连接 32 位浮点向量时，在行为仿真中一切顺利。但是，在综合后，“random_float”网络已被截断为 31 位。似乎“标志”被忽略了。有任何想法吗？

logic       [7:0]   exponent_seed      =   8'b01100101;
logic       [22:0]  mantissa_seed      =   23'b01001011101011110010100;
logic       [31:0]  random_float       =   32'b00000000000000000000000000000000;
logic       [7:0]   exponent           =   exponent_seed;
logic       [22:0]  mantissa           =   mantissa_seed;
logic               sign               =   1'b0;  

wire                exponent_feedback  =   exponent[7] ^ exponent[5] ^ exponent[4] ^ exponent[3];

always @ (exponent or mantissa or sign)
    begin
        random_float <= {sign, exponent, mantissa};
    end

 always @ (posedge clk or posedge reset)
    begin
        if (reset)
            begin
                exponent        <= exponent_seed;
                mantissa        <= mantissa_seed;
            end
         else
            begin
                //use concatenation to shift and feed the vector.
                exponent <= {exponent[6:0], exponent_feedback};
                mantissa <= {mantissa[21:0], mantissa_feedback};
            end
    end        

PS我只包含了我认为是相关代码的内容。

Answer 1

对于后代，以下内容会阻止综合优化常量：

(*KEEP = "TRUE"*) logic       [31:0]  random_float       =   32'b00000000000000000000000000000000;