caching - 没有 RAM 级 ECC 的缓存级 ECC 有什么意义？

Question

这是在零件选择交易中出现的。一些 ARM 单片机具有缓存级 ECC，但没有 RAM 级 ECC。似乎任何受 ECC 保护的系统都与其最薄弱的环节一样强大。我只缺少缓存级 ECC 是否有理由？

Answer 1

That is odd! You're right that the DRAM error cross-section is typically larger than the on-chip one, so DRAM is the "weakest link." (Assuming you have a large main memory.)

One possible explanation would be that they use the on-chip ECC for yield improvement, rather than directly for resilience. ECC on caches can be used to tolerate permanent faults in the cache SRAM bits, for instance, allowing the product to be shipped with the cache still enabled.