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我是一名学生，我必须根据此文档XAPP213创建一个 PicoBlaze 8 位微控制器。

当我必须运行跳转或调用指令时出现问题：

当我跳转或调用下一条指令时，我被迫成为 NULL 指令，因此我的程序计数器（女巫给了我我的新地址）保持相同的含义，即他持有相同地址 2 个时钟，并且读取指令的两倍女巫我跳了或我打电话。

我能做些什么不让这种情况发生？

如果有帮助，这是我的程序计数器代码：

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;

entity DL_PROGRAM_COUNTER is
     port(
         SELECT_1 : in BIT;
         SELECT_0 : in BIT;
         CARRY_IN : in BIT;
         CLK : in BIT;
         RESET : in BIT;
         ADR : in BIT_VECTOR(7 downto 0);
         IESIRE_STACK : in BIT_VECTOR(7 downto 0);
         ADDRESS : out BIT_VECTOR(7 downto 0)
         );
end DL_PROGRAM_COUNTER;

--}} End of automatically maintained section

architecture DL_A_PROGRAM_COUNTER of DL_PROGRAM_COUNTER is
component DL_GENERIC_MUX is 
    generic (Numar_biti_selectie: NATURAL :=1; Numar_biti_cale_date: NATURAL:=1);

    port (date: in BIT_VECTOR(0 to (2**Numar_biti_selectie)*Numar_biti_cale_date - 1);  -- date <= a0 & a1
          sel: in BIT_VECTOR(Numar_biti_selectie-1 downto 0);
          Y: out BIT_VECTOR(Numar_biti_cale_date-1 downto 0)
          );
end component;

component DL_GENERIC_REGISTRU_PASTRARE is
    port(date: in BIT_VECTOR(7 downto 0);
         clk,ce,reset: in BIT;
         Q: out BIT_VECTOR(7 downto 0)
        );
end component;

signal intermediar,iesire_1,iesire_0,aresa_urmatoare: BIT_VECTOR(7 downto 0);
signal date1,date0: BIT_VECTOR(0 to 15);
signal sel1,sel0: BIT_VECTOR(0 downto 0);

begin

COPIERE1: process(intermediar,ADR)
begin
    for k in 0 to 7 loop
        date1(k) <= intermediar(7-k);
        date1(8+k) <= ADR(7-k);
    end loop;
end process;
sel1(0) <= SELECT_1; 

MUX1: DL_GENERIC_MUX generic map(1,8) port map(date1,sel1,iesire_1);

COPIERE0: process(iesire_1,IESIRE_STACK)
begin
    for k in 0 to 7 loop
        date0(k) <= iesire_1(7-k);
        date0(8+k) <= IESIRE_STACK(7-k);
    end loop;
end process;
sel0(0) <= SELECT_0;

MUX2: DL_GENERIC_MUX generic map(1,8) port map(date0,sel0,iesire_0);

ADDER:process(iesire_0,CARRY_IN)
variable rez: INTEGER;
begin
    rez := CONV_INTEGER(TO_STDLOGICVECTOR(iesire_0));
    if CARRY_IN = '1' then
        rez := rez + 1; 
    end if;
    aresa_urmatoare <= TO_BITVECTOR(STD_LOGIC_VECTOR(TO_UNSIGNED(rez, aresa_urmatoare'length)));
end process;

REGISTRU: DL_GENERIC_REGISTRU_PASTRARE port map(aresa_urmatoare,CLK,'1',RESET,intermediar);

ADDRESS <= intermediar;

end DL_A_PROGRAM_COUNTER;

这是它的外观框图： 程序计数器框图

跳跃：

select_1 <= '1';
select_0 <= '0';
carry_in <= '0';

来电：

select_1 <= '1';
select_0 <= '0';
carry_in <= '0';

对于 NULL 指令：

select_1 <= '0';
select_0 <= '0';
carry_in <= '0';
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