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我正在使用 VHDL 进行秒表项目，但我不知道如何制作计数器的 CLK 方波？请帮忙。

这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

 entity Circuit is
    Port ( CLK : in  STD_LOGIC := '0';
           CLR : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (5 downto 0));
end Circuit;

architecture Behavioral of Circuit is

signal s: STD_LOGIC_VECTOR := "000000";

begin

process (CLK, CLR)
begin
if rising_edge(CLK) then
if CLR = '1' OR s = "111011" then
s <= "000000";
else
s <= s+1;
end if;
end if;
end process;
Q <= s;
end Behavioral;
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1 回答 1

2

假设您的时钟为 1 MHz，但您希望秒计数器进程以 1 Hz 工作。您需要将传入时钟除以 100 万。

constant CLOCK_DIVIDER : integer := 1000000;
signal clock_divide_counter : integer range 0 to CLOCK_DIVIDER-1 := 0;
signal one_hz_pulse : std_logic := '0';

...

process (clk)
begin
    if (rising_edge(clk)) then
        if (clock_divide_counter = CLOCK_DIVIDER - 1) then
            clock_divide_counter <= 0;
            one_hz_pulse <= '1';
        else
            clock_divide_counter <= clock_divide_counter + 1;
            one_hz_pulse <= '0';
        end if;
    end if;
end process;

然后修改您现有的进程，使其仅在 1 Hz 脉冲为高电平时启用：

process (CLK, CLR)
begin
    if rising_edge(CLK) then
        if (CLR = '1') then
            s <= "000000";
        elsif (one_hz_pulse = '1') then
            if s = "111011" then
                s <= "000000";
            else
                s <= s+1;
            end if;
        end if;
    end if;
end process;

我没有运行代码，但你应该明白了。

于 2015-04-29T15:30:47.230 回答