fpga - Can I access delayed value in SystemVerilog assertion

Question

I want to use an old value of a signal in a SystemVerilog assertion.

This is what I am currently doing

logic [ADDRESS_WIDTH-1:0] old_address [1:0];

always_ff@(posedge rdclock) begin
   old_address[0] <= rdaddress;
   old_address[1] <= old_address[0];
end

property FooBar;
   @(posedge rdclock) rden |-> ##2 q == mem[old_address[1]];
endproperty

Baz: assert property (FooBar);

Is this how is should be done, or can I somehow use an old version of rdaddress directly in the assertion?

Answer 1

您可以使用$past(...)系统任务。使用$past(rdaddress)将返回rdaddress在上一个周期中采样的值。您可以使用第二个参数指定过去多少个周期。在您的情况下，调用$past(rdaddress, 2)将返回rdaddress2 个周期之前的值。