I have to design a 1 bit ALU for an assignment which would then be reused to make 4 units and a 4 bit ALU.
1 bit ALU has 2 select lines and inputs A, B and a carry in.
My problem is that the select lines AND the carry in flag choose what operation to select. I just have no clue how to use the select lines and carry flag at the same time to select the operation.
For example, select lines "00" and Cin "0" is an add operation whereas Cin "1" is a subtract.
Could I do what I have done below? Thanks for your help.
entity ALU1Bit is
port(
A: IN std_logic_vector;
B: IN std_logic;
carryIn: IN std_logic;
operation: IN std_logic_vector(1 downto 0);
F: OUT std_logic;
carryOut: OUT std_logic
);
end ALU1Bit;
architecture Behavioral of ALU1Bit is
component Adder1Bit
port(
carryIn: IN std_logic;
A: IN std_logic;
B: IN std_logic;
output: OUT std_logic;
F: OUT std_logic
);
end component;
begin
carryIn <= '0';
case operation is
when...
carryIn <= '1';
case operation is
when...
end Behavioral;