I am having this issues in the Cadence tool chain simulation when I try to connect the multidimensional user defined type in VHDL to SystemVerilog in a UVM environment. This is the VHDL output type definition:
TYPE loop_reg_ty IS RECORD
loop_index_value : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
loop_counter : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
loop_end_flag : std_logic;
END RECORD;
TYPE loop_array_ty is array (MAX_NO_OF_LOOPS-1 downto 0) of loop_reg_ty;
One of the VHDL output ports in my DUT is of type loop_array_ty
;
I am trying to define the SystemVerilog equivalent as:
typedef struct packed {
bit [REG_BITWIDTH-1:0] loop_index_value;
bit [REG_BITWIDTH-1:0] loop_counter;
bit loop_end_flag;
} raccu_loop_reg_ty;
typedef raccu_loop_reg_ty [MAX_NO_OF_RACCU_LOOPS-1:0] loop_array_ty;
When I use irun
, I get the error:
VHDL port type is not compatible with Verilog.
Please suggest the possible work around solution.