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I am having this issues in the Cadence tool chain simulation when I try to connect the multidimensional user defined type in VHDL to SystemVerilog in a UVM environment. This is the VHDL output type definition:

TYPE loop_reg_ty IS RECORD
      loop_index_value    : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
      loop_counter : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
      loop_end_flag : std_logic;
END RECORD;

TYPE loop_array_ty is array (MAX_NO_OF_LOOPS-1 downto 0) of loop_reg_ty;

One of the VHDL output ports in my DUT is of type loop_array_ty;

I am trying to define the SystemVerilog equivalent as:

typedef struct packed {
                            bit [REG_BITWIDTH-1:0] loop_index_value;
                            bit [REG_BITWIDTH-1:0] loop_counter;
                            bit loop_end_flag;
                          } raccu_loop_reg_ty;

typedef raccu_loop_reg_ty [MAX_NO_OF_RACCU_LOOPS-1:0] loop_array_ty;

When I use irun, I get the error:

VHDL port type is not compatible with Verilog.

Please suggest the possible work around solution.

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1 回答 1

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首先,您的问题是您没有loop_array_ty正确定义。应该是typedef raccu_loop_reg_ty loop_array_ty[MAX_NO_OF_RACCU_LOOPS-1:0]

我会在这里建议两件事:

首先,尝试从定义中删除packed限定符。struct将 SV 结构连接到 VHDL 记录仅在较新的 Incisive 版本中可用。确保您使用的版本支持此功能。

如果您使用的是旧版本的 Incisive(就像我在一年前一样),您唯一的选择是使用$nc_mirror(未经测试的代码,但足以让您入门)映射各个记录成员:

// struct definition...
// ...

module top;
  // intermediate signal we'll mirror onto
  loop_array_ty loop_s;

  // no output connected
  my_dut dut_inst();

  // make the connection between SV and VHDL using nc_mirror
  initial begin
    for (int i = 0; i < MAX_NO_OF_RACCU_LOOPS; i++) begin
      $nc_mirror($sformatf("loop_s[%0d].loop_index_value", i),
        $sformatf("dut_inst.loop_o[%0d].loop_index_value", i);

      // $nc_mirror for loop_counter
      // $nc_mirror for loop_end_flag
    end
  end
endmodule

还要确保您REG_BITWIDTH在两种语言中都正确设置了常量,否则您也会得到类型不匹配。

于 2014-12-05T19:33:57.320 回答