verilog - 电路在时序仿真中表现不佳，但在行为方面表现良好 - verilog 的新手

Question

我是 Verilog 开发的新手，在相对简单的计数器和触发器输出类型设计上看不到哪里出错了。

这是verilog代码 请注意，无论reg是否在没有internal_output_buffer的output_signal上声明，代码都会返回相同的结果

    `timescale 1ns / 1ps

module testcounter(
        input wire clk,
        input wire resetn,
        input wire [31:0] num_to_count,
        output reg [7:0] output_signal
    );

    reg [31:0] counter;

    initial begin
        output_signal = 0;
    end

    always@(negedge resetn) begin
        counter = 0;
    end

    always@(posedge clk) begin
        if (counter == num_to_count) begin
            counter = 0;
            if (output_signal == 0) begin
                output_signal = 8'hff;
            end
            else begin
                output_signal = 8'h00;
            end
        end
        else begin
            counter = counter + 1;
        end 


    end
    assign output_signal = internal_output_buffer;

endmodule

并且代码经过测试

 `timescale 1ns / 1ps

module testcounter_testbench(

    );
    reg clk;
    reg resetn;
    reg [31:0] num_to_count;
    wire [7:0] output_signal;

    initial begin
        clk = 0;
        forever #1 clk = ~clk;
    end

    initial begin
        num_to_count = 20;
    end

    initial begin
        #7 resetn = 1;
        #35 resetn = 0;
    end

    testcounter A1(.clk(clk),.resetn(resetn),.num_to_count(num_to_count),.output_signal(output_signal));
endmodule

行为模拟看起来和我预期的一样

但是时序模拟爆炸了

并且为了更好的衡量：实际探测的执行爆炸了，看起来像

任何提示将不胜感激。谢谢大家。

Answer 1

您的代码使用 Xilinx Vivado 14.2 似乎工作正常，但只有一个错误，即以下行

assign output_signal = internal_output_buffer;

您不能使用“assign”来分配寄存器，并且“internal_output_buffer”也没有定义。

我个人还建议在初始时将所有寄存器设置为某些值。您的变量“resetn”和“counter”最初没有分配。例如，基本上像这样更改您的代码

reg [31:0] counter = 32'b0;

这是我的代码结果：

Answer 2

The difference between the timing and functional simulations is that a timing simulation models the actual delay of logic gates while the functional simulation just checks if values are correct.

For e.g. if you have a simple combinational adder with two inputs a and b, and output c. A functional simulation will tell you that c=a+b. and c will change in the exact microsecond that a or b changes. However, a timing simulation for the same circuit will only show you the result (a+b) on c after some time t, where t is the delay of the adder.

What is your platform? If you are using an FPGA it is very difficult to hit 500 MHz. Your clock statement:

    forever #1 clk = ~clk;

shows that you toggle the clock every 1ns, meaning that your period is 2ns and your frequency is 500MHz.

The combinational delay through FPGA resources such as lookup tables, multiplexers and wire segments is probably more than 2ns. So your circuit violates timing constraints and gives wrong behaviour.

The first thing I would try is to use a much lower clock frequency, for example 100 MHz and test the circuit again. I expect it to produce the correct results.

    forever #5 clk = ~clk;

Then to know the maximum safe frequency you can run at, look at your compilation reports in your design tools by running timing analysis. It is available in any FPGA CAD tool.

Answer 3

您在 testcounter 中的 verilog 代码看起来已损坏：（a）您有多个驱动程序，并且（b）像 @StrayPointer 通知一样，您正在使用阻塞分配来分配寄存器（触发器）值。

我猜您的意图如下，这可以解决很多模拟不匹配问题：

module testcounter
(
    input wire clk,
    input wire resetn,
    input wire [31:0] num_to_count,
    output reg [7:0] output_signal
);

reg [31:0] counter;

always@(posedge clk or negedge resetn) begin
    if (!resetn) begin
        counter <= 0;
    end else begin
        if (counter == num_to_count) begin
            counter <= 0;
        end else begin
            counter <= counter + 1;
        end
    end
end
assign output_signal = (counter == num_to_count) ? 8'hff : 8'h00;

endmodule