riscv - Rocket core实现了RISCV的RV64G版本？

Question

我想知道，哪个版本的 riscv ISA 是发布的能够实现的火箭核心。

由于它支持双精度浮点，我可以安全地假设它是 RV64G 版本。

Answer 1

Yes, the Rocket core implements RV64G.*

If you'd like to manually verify this yourself, you can check the ctrl code's decode tables.

However, you can turn off the FPU in the parameter settings of the rocket-chip generator, by setting case BuildFPU =>... to None (or by invoking the SmallConfig when building Rocket from the command line).

Fun fact, in inspecting the decode tables, you can also see additional custom extension instructions used to implement the "RoCC" interface, which communicates with any attached accelerator/co-processor cores ("ROcket Coprocessor Coordination"). By default they are off, as buildROCC is set to None.

*Edit: As you point out, Rocket (currently) eschews implementing the fdiv and fsqrt instructions. These will trap and will be executed in software (assuming you are running Rocket on top of a kernel that implements these instructions). In fact, the current riscv-gcc port will not emit these instructions by default, but will instead emit soft-float versions on fdiv and fsqrt.

References

• ctrl code
• parameter/configuration file
• core code
• chip code