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所以我正在尝试设计七段解码器。在 110 按下按钮时，LED 显示屏应显示 1 位十六进制数：0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F。但是，当在 101 处按下 Button 时，LED 显示屏应显示 1 位十进制数：0,1,2,3,4,5,6,7,8,9。

这是我的警告：

Xst:737 - Found 1-bit latch for signal <out<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

这是我使用 Xilinx 设计工具的代码：

module hex_sch(out, in, button);
output reg [6:0] out;
input [3:0] in;
input [2:0] button;
// Low active signal should activate the LEDs
    always @(button or in) 
    begin
        if (button == 3'b110) begin
            case (in)
            //Output format gfedcba
            4'h0: out <= 7'b1000000;
            4'h1: out <= 7'b1111001;
            4'h2: out <= 7'b0100100;
            4'h3: out <= 7'b0110000;
            4'h4: out <= 7'b0011001;
            4'h5: out <= 7'b0010010;
            4'h6: out <= 7'b0000010;
            4'h7: out <= 7'b1111000;
            4'h8: out <= 7'b0000000;
            4'h9: out <= 7'b0011000;
            4'hA: out <= 7'b0001000;
            4'hB: out <= 7'b0000011;
            4'hC: out <= 7'b1000110;
            4'hD: out <= 7'b0100001;
            4'hE: out <= 7'b0000110;
            4'hF: out <= 7'b0001110;
            default: out <= 7'bx;
            endcase
            end
        else if (button == 3'b101) begin
            case (in)
            //Output format abcdefg
            4'd0: out <= 7'b1000000;
            4'd1: out <= 7'b1111001;
            4'd2: out <= 7'b0100100;
            4'd3: out <= 7'b0110000;
            4'd4: out <= 7'b0011001;
            4'd5: out <= 7'b0010010;
            4'd6: out <= 7'b0000010;
            4'd7: out <= 7'b1111000;
            4'd8: out <= 7'b0000000;
            4'd9: out <= 7'b0011000;
            default out <= 7'bx;
            endcase
            end
    end
endmodule
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1 回答 1

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为了消除这些警告，您必须为out所有可能的in和设置一个值button。否则你会得到一个闩锁。

在您的代码中，您并未涵盖button输入的所有可能性 - 您仅涵盖 110 和 101。

涵盖代码中所有可能性的简单方法可能是：

... // 你的模块定义原样

// 低电平有效信号应该激活 LED

always @(button or in) 
begin
    if (button == 3'b110) begin
        case (in)
        //Output format gfedcba

... // 你的 case 语句原样

        endcase
    end
    else if (button == 3'b101) begin
        case (in)

... // 你的 case 语句原样

        endcase
    end
    else begin
        out <= 7'b1;
    end
end endmodule

这样，当按钮与 110 或 101 不同时，它将显示为空白。

于 2014-10-19T08:40:59.913 回答