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我正在尝试为 4 位通用移位寄存器制作 VHDL 代码，我想在其中加载 4 位并从 ctrl 中选择移位操作。我不知道如何实现时钟分频器以在 FPGA 上运行输出。

到目前为止，这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity shift_register is
  generic(N : integer := 4);
  port(
    clk, reset : in  std_logic;
    ctrl       : in  std_logic_vector(1 downto 0);
    d          : in  std_logic_vector((N-1) downto 0);
    q          : out std_logic_vector((N-1) downto 0)
    );
end shift_register;

architecture Behavioral of shift_register is

  signal r_reg  : std_logic_vector((N-1) downto 0);
  signal r_next : std_logic_vector((N-1) downto 0);
begin
  process(clk, reset)
  begin
    if(reset = '1') then
      r_reg <= (others => '0');
    elsif(clk'event and clk = '1') then
      r_reg <= r_next;
    end if;
  end process;

  with ctrl select
    r_next <=
    r_reg                      when "00",   --do nothing
    r_reg(N-2 downto 0) & d(0) when "01",   --shift left
    d(N-1) & r_reg(N-1 downto 1)when "10",  --shift right
                     d when others;         --load

  q <= r_reg;
end Behavioral;
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1 回答 1

2

每个时钟周期enable断言一个周期的分频器代码模板：RATIO

library ieee;
use ieee.numeric_std.all;

architecture syn of mdl is
  constant RATIO  : natural := 10;
  signal prescale : std_logic_vector(9 downto 0);  -- Scale to fit RATIO - 1
  signal enable   : std_logic;
begin

  process (clk, reset) is
  begin
    if reset = '1' then
      enable   <= '0';
      prescale <= std_logic_vector(to_unsigned(RATIO - 1, prescale'length));
    elsif rising_edge(clk) then
      if unsigned(prescale) = 0 then
        enable   <= '1';
        prescale <= std_logic_vector(to_unsigned(RATIO - 1, prescale'length));
      else
        enable   <= '0';
        prescale <= std_logic_vector(unsigned(prescale) - 1);
      end if;
    end if;
  end process;

end architecture;
于 2014-09-19T13:34:32.337 回答