system-verilog - Illegal assignment to class mtiUvm.uvm_pkg::uvm_component

Question

I get this error when trying to access the uvm_config_db to access a variable. I googled it and found the following answer on the accellera forums:

http://forums.accellera.org/topic/406-compilation-error-regarding-illegal-class-assignment/

You cannot use this as a context inside a sequence; you must rely on the full sequence name.

Can anyone explain why this is so? Thanks

Answer 1

uvm_config_db::get/set在您的情况下，您为上下文传递的值this必须引用 UVM 组件。根据context配置设置应用的完整层次路径的路径值构建。如果this是一个序列（不继承自uvm_component，那么它将没有固定的层次结构。

我通常按​​顺序做的是：

uvm_config_db #(some_type)::get(p_sequencer, "", "some_field", some_field);

p_sequencer是一个 UVM 组件，您可以将配置设置应用于在该定序器上启动的任何序列。