我已经尝试了 EDAPlayground.com 上 myHDL 手册中的以下代码，但它没有为我打印任何内容。谁能告诉我为什么？以及如何解决这个问题？
我在网站上的配置在此处概述。
测试台+设计：仅 Python 方法：MyHDL 0.8
从随机导入 randrange 从 myhdl 导入 *
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
def Inc(count, enable, clock, reset, n):
""" Incrementer with enable.
count -- output
enable -- control input, increment when 1
clock -- clock input
reset -- asynchronous reset input
n -- counter max value
"""
@always_seq(clock.posedge, reset=reset)
def incLogic():
if enable:
count.next = (count + 1) % n
return incLogic
def testbench():
count, enable, clock = [Signal(intbv(0)) for i in range(3)]
# Configure your reset signal here (active type, async/sync)
reset = ResetSignal(0,active=ACTIVE_LOW,async=True)
## DUT to be instantiated
inc_1 = Inc(count, enable, clock, reset, n=4)
HALF_PERIOD = delay(10)
## forever loop : clock generator
@always(HALF_PERIOD)
def clockGen():
clock.next = not clock
## Stimulus generator
@instance
def stimulus():
reset.next = ACTIVE_LOW
yield clock.negedge
reset.next = INACTIVE_HIGH
for i in range(12):
enable.next = min(1, randrange(3))
yield clock.negedge
raise StopSimulation
@instance
def monitor():
print "enable count"
yield reset.posedge
while 1:
yield clock.posedge
yield delay(1)
print " %s %s" % (enable, count)
return clockGen, stimulus, inc_1, monitor
tb = testbench()
def main():
Simulation(tb).run()