我正在尝试使用结构代码在 VHDL 中构建一个异或门。我使用其他方法构建了相同的门，以使用测试台比较输出。
这是 xor_structural.vhdl 文件。我自己构建了and、or 和nand。我认为他们不需要进入单独的文件，因为它编译得很好。该文件和测试台编译没有问题，但我无法运行模拟。
测试台和其他模拟效果很好，但是当我尝试运行模拟时，出现以下错误。
我认为我缺少一些关于结构代码的东西。
vsim work.antivalenz_tb
# vsim work.antivalenz_tb
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(51): (vopt-3473) Component instance "u0 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(52): (vopt-3473) Component instance "u1 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(53): (vopt-3473) Component instance "u2 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(54): (vopt-3473) Component instance "u3 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(55): (vopt-3473) Component instance "u4 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(56): (vopt-3473) Component instance "u5 : nand2" is not bound.
# ** Error: /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(51): No default binding for component instance "u0 : nand2".
# (Component port "out1" is not on the entity.)
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(57): (vopt-3473) Component instance "u6 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(59): (vopt-3473) Component instance "d0 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(60): (vopt-3473) Component instance "d1 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(61): (vopt-3473) Component instance "d2 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(62): (vopt-3473) Component instance "d3 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(63): (vopt-3473) Component instance "d4 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(64): (vopt-3473) Component instance "d5 : or2" is not bound.
# ** Error: /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(59): No default binding for component instance "d0 : or2".
# (Component port "out1" is not on the entity.)
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(65): (vopt-3473) Component instance "d6 : or2" is not bound.
# ** Error: /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(67): No default binding for component instance "x1 : and2".
# (Component port "out1" is not on the entity.)
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(67): (vopt-3473) Component instance "x1 : and2" is not bound.
# Optimization failed
# Error loading design
Xor_struktur.vhdl entity and2 是端口（A, B : in bit; Y : out bit）；最终实体和2；
architecture logic of and2 is
begin
Y <= (A and B);
end architecture logic;
entity or2 is
port(A, B : in bit;
Y : out bit);
end entity or2;
architecture logic of or2 is
begin
Y <= A or B;
end architecture logic;
entity nand2 is
port (A, B : in bit;
Y : out bit);
end entity nand2;
architecture logic of nand2 is
begin
Y <= not(A and B);
end architecture logic;
entity antivalenz_struktur is
port ( a , b : in bit_vector(0 to 3) ;
Y : out bit ) ;
end entity antivalenz_struktur ;
architecture struktur of antivalenz_struktur is
component and2
port (a, b: in bit;
out1: out bit);
end component;
component nand2
port (a, b: in bit;
out1: out bit);
end component;
component or2
port (a, b: in bit;
out1: out bit);
end component;
signal s0,s1,s2,s3,s4,s5,s6,s7,nand_out,a0,a1,a2,a3,a4,a5,a6,a7,or_out:bit;
begin
U0: nand2 port map (a(0),b(0),s0);
U1: nand2 port map (a(1),b(1),s1);
U2: nand2 port map (a(2),b(2),s2);
U3: nand2 port map (a(3),b(3),s3);
U4: nand2 port map (s0,s1,s4);
U5: nand2 port map (s2,s3,s5);
U6: nand2 port map (s4,s5,nand_out);
D0: or2 port map (a(0),b(0),a0);
D1: or2 port map (a(1),b(1),a1);
D2: or2 port map (a(2),b(2),a2);
D3: or2 port map (a(3),b(3),a3);
D4: or2 port map (a0,a1,a4);
D5: or2 port map (a2,a3,a5);
D6: or2 port map (a4,a5,or_out);
X1: and2 port map (nand_out,or_out,Y);
end architecture struktur;
测试台文件
entity antivalenz_tb is
end antivalenz_tb;
architecture behavior of antivalenz_tb is
signal a, b : bit_vector (0 to 3);
signal Y_Dataflow : bit;
signal Y_Logic: bit;
signal Y_Behavior: bit;
signal Y_Structure: bit;
begin
dut: entity work.antivalenz_datenfluss(datenfluss)
port map(a => a,
b => b,
Y => Y_Dataflow);
dut1: entity work.antivalenz_logic(logic)
port map(a => a,
b => b,
Y => Y_Logic);
dut2: entity work.antivalenz_verhalten(behavior)
port map(a => a,
b => b,
Y => Y_Behavior);
dut3: entity work.antivalenz_struktur(struktur)
port map(a => a,
b => b,
Y => Y_Structure);
a <= "0000",
"1111" after 10 ns,
"1010" after 20 ns,
"0101" after 30 ns,
"1100" after 40 ns;
b <= "0000",
"1111" after 10 ns,
"0101" after 20 ns,
"1010" after 30 ns,
"0011" after 40 ns;
end behavior;