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我真的很不同，我需要你的帮助！首先，这是我在数字系统设计方面的第一门课程，我们被要求做一些项目，它是一个 ALU（算术逻辑单元），它执行多项操作，如加法、减法、递增、递减、2 的补码和一些逻辑门。 ..但是在完成所有工作并尝试模拟项目后，我将所有输出都设为“未知”..

这是截图：

这是 ALU 代码：

    Library IEEE;
use IEEE.std_logic_1164.all;

entity raja_hussein is
  port( A , B : IN std_logic_vector( 15 downto 0 ) ;
    Cin : IN std_logic;
    S : IN std_logic_vector( 2 downto 0 );
    Y : OUT std_logic_vector( 15 downto 0 );
    C,O,N,Z : OUT std_logic
  );
end raja_hussein ;

architecture raja_hussein_arch of raja_hussein is

  component adder16bit 
    port (
        X  : in  STD_LOGIC_VECTOR(15 downto 0);
        Y  : in  STD_LOGIC_VECTOR(15 downto 0);
        C0 : in  STD_LOGIC;
        S  : out STD_LOGIC_VECTOR(15 downto 0);
        C16: out STD_LOGIC;
        O,N,Z : out std_logic
    );
  end component;

  component DEMUX1to2 
    port(
     S : IN std_logic;
     I : IN std_logic;
     A : OUT std_logic;
     B : OUT std_logic
    );
  end component;

  component DEMUX1to4 
    port( S : IN std_logic_vector( 1 downto 0);
    I : IN std_logic;
    A,B,C,D : OUT std_logic
    );
  end component;

  component MUX2to1 
    Port ( S : IN STD_LOGIC;
        A, B: IN STD_LOGIC_VECTOR( 1 TO 16) ;
        Y : OUT STD_LOGIC_VECTOR(1 TO 16) 
    ) ;
   end component;

   component MUX4to1
     Port ( S :IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
         A, B, C, D : IN STD_LOGIC_VECTOR( 1 TO 16) ;
         Y :OUT STD_LOGIC_VECTOR(1 TO 16) 
     ) ;
   end component;

   component ANDGATE
     port (X, Y: IN STD_LOGIC_vector(15 downto 0);
          EN: IN std_logic;
            Z     : OUT STD_LOGIC_vector(15 downto 0)
      );
    end component;

    component ORGATE
      port (X, Y : IN STD_LOGIC_vector(15 downto 0);
          EN : in std_logic;
            Z     : OUT STD_LOGIC_vector(15 downto 0)
      );
    end component;

    component XORGATE
      port (X, Y: IN STD_LOGIC_vector(15 downto 0);
          en: in std_logic;
            Z     : OUT STD_LOGIC_vector(15 downto 0)
      );
    end component;

    component bitinverter
      port (x : in STD_LOGIC_VECTOR(1 to 16);
            y : out STD_LOGIC_VECTOR(1 to 16)
       );
     end component;

     component MUX4to1_1bit
       Port ( S :IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
         A, B, C, D : IN STD_LOGIC ;
         Y :OUT STD_LOGIC  
      ) ;
    end component;

     signal X : std_logic_vector( 0 to 14 ) := (others =>'0') ;
     signal Binv : std_logic_vector( 15 downto 0 ) := (others =>'0');
     signal L, M : std_logic_vector( 15 downto 0) := (others =>'0');
     signal R : std_logic := '0';
     signal zero : std_logic_vector( 15 downto 0 ) := "0000000000000000";
     signal one : std_logic_vector( 15 downto 0) := "0000000000000001";
     signal oneinv: std_logic_vector( 15 downto 0 ) := "1111111111111110";
     signal one_1bit : std_logic := '1';
     signal zero_1bit : std_logic := '0' ;

     begin
       U1 : DEMUX1to2 port map( one_1bit , S(2) , X(0) , X(1) );
       U2 : DEMUX1to4 port map( S(1 downto 0) ,X(0) ,  X(2) , X(3) , X(4) , X(5) );
       U3 : DEMUX1to4 port map( S(1 downto 0) ,X(1) ,  X(6) , X(7) , X(8) , X(9) );
       U4 : MUX2to1 port map( X(3) ,A , zero ,  L );
       U5 : bitinverter port map ( B , Binv );
       X(11) <= (X(4) or X(5)) ;
       X(12) <= (X(2) or X(3) or X(5));
       U6 : MUX4to1 port map ( X( 11 to 12) , B , Binv , one , oneinv , M ) ;
       X(13) <= X(4) ;
       X(14) <= X(12);
       U7 : MUX4to1_1bit port map ( X(13 to 14) , Cin , one_1bit , zero_1bit , zero_1bit , R );
       U8 : ANDGATE port map( A , B , X(6) , Y ) ;
       U9 : ORGATE port map ( A , B , X(7) , Y );
       U10: XORGATE port map ( A, B , X(8) , Y );
       U11: adder16bit port map ( L , M , R , Y , C , O , N , Z );
      end raja_hussein_arch;

这是测试台：

 Library IEEE;
use IEEE.std_logic_1164.all;

entity raja_hussein_TB is
end raja_hussein_TB;

architecture raja_hussein_TB_arch of raja_hussein_TB is
  component raja_hussein
     port( A , B : IN std_logic_vector( 15 downto 0 ) ;
    Cin : IN std_logic;
    S : IN std_logic_vector( 2 downto 0 );
    Y : OUT std_logic_vector( 15 downto 0 );
    C,O,N,Z : OUT std_logic
    );
  end component;

  signal A,B,Y : std_logic_vector( 15 downto 0 ) ;
  signal Cin,C,O,N,Z : std_logic ;
  signal S : std_logic_vector( 2 downto 0 ) ;

  begin
    UTT: raja_hussein port map( A,B,Cin,S,Y,C,O,N,Z);

      process
        begin
          A <= "0000000000000000"; B <= "0000000000000000" ; S <= "000" ; Cin <= '0' ; wait for 20 ns;
          A <= "0000000000000000"; B <= "0000000000000000" ; S <= "001" ; Cin <= '0' ; wait for 20 ns;
          A <= "0000000000000000"; B <= "0000000000000000" ; S <= "010" ; Cin <= '0' ; wait for 20 ns;
          A <= "0000000000000000"; B <= "0000000000000000" ; S <= "011" ; Cin <= '0' ; wait for 20 ns;
          A <= "0000000000000000"; B <= "0000000000000000" ; S <= "100" ; Cin <= '0' ; wait for 20 ns;
          A <= "0000000000000000"; B <= "0000000000000000" ; S <= "101" ; Cin <= '0' ; wait for 20 ns;
          A <= "0000000000000000"; B <= "0000000000000000" ; S <= "110" ; Cin <= '0' ; wait for 20 ns;
          A <= "0000000000000000"; B <= "0000000000000000" ; S <= "111" ; Cin <= '0' ; wait for 20 ns;

          A <= "0101010101010101"; B <= "0110101101110011" ; S <= "000" ; Cin <= '0' ; wait for 20 ns;
          A <= "0101010101010101"; B <= "0110101101110011" ; S <= "001" ; Cin <= '0' ; wait for 20 ns;
          A <= "0101010101010101"; B <= "0110101101110011" ; S <= "010" ; Cin <= '0' ; wait for 20 ns;
          A <= "0101010101010101"; B <= "0110101101110011" ; S <= "011" ; Cin <= '0' ; wait for 20 ns;
          A <= "0101010101010101"; B <= "0110101101110011" ; S <= "100" ; Cin <= '0' ; wait for 20 ns;
          A <= "0101010101010101"; B <= "0110101101110011" ; S <= "101" ; Cin <= '0' ; wait for 20 ns;
          A <= "0101010101010101"; B <= "0110101101110011" ; S <= "110" ; Cin <= '0' ; wait for 20 ns;
          A <= "0101010101010101"; B <= "0110101101110011" ; S <= "111" ; Cin <= '0' ; wait for 20 ns;
        end process;
      end raja_hussein_TB_arch;

知道可能是什么问题吗？

谢谢大家:)

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