Please note, this is a study question.
I have to describe a simple d-latch in vhdl, and then synthesize it. The problem is that it is a "unary" d-latch, and its single input is mapped directly to its outputs (Q and nQ). You can imagine it as a classical async d-latch, where clk signal is always high. This is useless element in logic, and xilinx synthesizer in most cases gives an empty technology schema. But the reason to keep this element is, for example, creating hardware "watermarks", which present on the schema, but don't affect its logic.
I came up with the following code:
entity dLatch is
port(
d: in std_logic;
q: out std_logic);
end dLatch;
architecture dLatch_beh of dLatch is
signal o: std_logic;
begin
latch: process(d)
begin
if d = '1' then
o <= '1';
elsif d = '0' then
o <= '0';
end if;
end process;
q <= o;
end;
This code produce the following technology schema
But when I try to add nQ out port, I gain duplication of latch
entity dLatch is
port(
d: in std_logic;
q, nq: out std_logic);
end dLatch;
architecture dLatch_beh of dLatch is
signal o: std_logic;
begin
latch: process(d)
begin
if d = '1' then
o <= '1';
elsif d = '0' then
o <= '0';
end if;
end process;
q <= o;
nq <= not o;
end;
Technology schema: link
I don't understand, why I am getting two completely equal latches here. I expected only one additional 'not' gate. So my question is how to avoid the duplication of latches, or maybe some other way to solve this problem. I use Xilinx ISE Web Pack 14.6 for synthesis.
UPD The solution is to set synthesizer's flag -register_duplication to false.