vhdl - VHDL 奇怪的行为

Question

我有这行代码：

entity test is
    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
              c : out  STD_LOGIC_VECTOR (15 downto 0));
end test;

architecture Behavioral of test is

component adder is
    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           s : out  STD_LOGIC_VECTOR (7 downto 0));
end component;

signal prod: std_logic_vector (15 downto 0) :=X"0000";
signal tempsum1,tempsum2: std_logic_vector (7 downto 0):=X"00";
signal cin,cout:std_logic:='0';

begin

--Working(modelsim can see the upper value of c)

S1: adder port map(tempsum1, prod(15 downto 8), c(15 downto 8));


--Not working(c gets a red line on all bits):
--I replace the first S1 with this one and assign later.
S1: adder port map(tempsum1, prod(15 downto 8), tempsum2);
c(15 downto 8)<=tempsum2;

end Behavioral;

有人能告诉我为什么在第一个代码块中 c 被正确设置并在 modelsim 中正确显示，而第二个代码块不是吗？谢谢你。

Answer 1

尝试在 tempsum2 的信号声明中抑制初始化。