verilog - Accessing inputs and outputs in sub-modules from testbench

Question

My device-under-test (DUT) has many sub-modules and I would like to test some of them.

My test fixture will be the top level of my project - one level higher than the DUT - and since I can only seem to access the inputs and outputs of the modules one level down, I can only access the top-level inputs and outputs of the DUT.

I would like to be able to access signals from the modules two or more levels beneath the test fixture, ideally without having to rewrite any modules to add more outputs so the signals I want to test are connected to the top level.

I could rewrite the device under test but this seems time-consuming and I feel there should be a quicker way.

Is there a way to write a test fixture that can access signals within sub-modules, without rewriting the DUT?

Answer 1

If you only need to monitor signals inside your top-level dut module, you can use hierarchical path specifiers to scope down into the dut:

dut.read_data

SystemVerilog also offers the bind statement to do something similar.

If you need to drive internal dut signals, you should create a separate testbench for the sub-module. This is more time-consuming, but gives you better control and allows you to achieve 100% coverage (which can sometimes be difficult at the top-level).