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我想设计一个计数到某个数字的计数器，假设它是 3，为此我编写了一个与"$finish"但不能与"disable"一起工作的代码。

我想用这个计数器进行综合，所以我必须使用“禁用”语句......

我附上了我的两个代码 - (1) 使用 $finish 可以轻松准确地停止

// Code with $finish   
module counter(input wire  clk);

reg [23:0]N=24'b0000_0000_0000_0000_0000_0000;

always @ (posedge clk)
 begin 

  if (N == 24'b0000_0000_0000_0000_0000_0011)
   begin 
    $display("Inside If N=%d in Time=",N,$time);
    $finish;
   end
   else 
   begin 
    N <= N +1;    
    $display("Inside Else N=%d in Time=",N,$time);
   end 
  end

endmodule

（2）禁用根本不会停止..

// Code with disable that not stop    
module counter(input wire  clk);

reg [23:0]N=24'b0000_0000_0000_0000_0000_0000;

always @ (posedge clk)
 begin :close

  if (N == 24'b0000_0000_0000_0000_0000_0011)
   begin 
    $display("Inside If N=%d in Time=",N,$time);
    disable close; 
  end
  else 
  begin 
    N <= N +1;    
    $display("Inside Else N=%d in Time=",N,$time);
  end 
 end

endmodule
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2 回答 2

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将 放在$finish测试台的末尾，而不是放在综合 RTL 中。

$finish停止所有正在运行的进程并结束模拟。disable停止一个进程及其子进程。在您的示例代码中，disable close终止始终块内的代码，它不会停止时钟。下一个上升沿时钟和 always 块将尝试再次运行。

有关声明，请参阅IEEE std 1800-2012 § 20.2$finish和有关 Disable 声明的 § 9.6.2

于 2013-10-16T19:06:24.930 回答
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toolic and Greg have both indicated to incorrect uses of $finish and disable, this is just to add to both of those points and show a possible solution, seperating test from synthesizable RTL.

module counter(input clk);

  reg [23:0] N = 24'b0;

  always @ (posedge clk) begin 
    if (N < 24'd3) begin 
      N <= N +1; 
      $display("Inside If N=%d in Time=",N,$time);
    end
    else begin 
      $display("Inside Else N=%d in Time=",N,$time);
    end 
  end
endmodule

To test it:

module test;

//Create clk
reg clk;
initial begin
  clk = 0 ;
  forever begin
    #5  clk =   ~clk;
  end
end

//instantiate DUT (Device Under Test)
counter counter_i0(
  .clk( clk )
);

// The test
//  Run for 6 clock cycles then end
initial begin
  repeat (6) begin
    @(posedge clk)
  end
  $finish;
end
endmodule

If you mean to stop at count 3, I would use decimal notation 24'd3 for the constant, as it gives clear intent.

also if using == to stop a counter a glitch could cause this to be missed and you have to wait for this to wrap arround. Or using a less than comparator means that the count target can be adjusted on the fly with out fear of skipping the exact value in == and having to wait a really long time for it to wrap around.

inputs are implicitly wires, no need to define them as such but you can if you want.

于 2013-10-16T19:28:31.020 回答