vhdl - 如何为原理图创建 VHDL 测试平台？

Question

我有简单的 VHDL 模块测试

entity test is 
 port( 
  clk: in std_logic;
  test_out: out std_logic
  ); 
end test;  

architecture Behavioral of test is
begin 
main: process(clk)
variable tmp_buffer : std_logic:='0';
begin
if (rising_edge(clk) and tmp_buffer='0') then
    test_out<='1';
    tmp_buffer:='1';
end if;
if (rising_edge(clk) and tmp_buffer='1') then
    test_out<='0';
    tmp_buffer:='0';
end if;
end process;
end Behavioral;

创建了简单的示意图

和用户约束文件（Spartan-3 XC3S200）：

NET "clk_port" LOC = "C5";
NET "test_out_port" LOC = "B5";

为原理图创建了测试台（！）

ENTITY main_main_sch_tb IS
END main_main_sch_tb;
ARCHITECTURE behavioral OF main_main_sch_tb IS 

   COMPONENT main
   PORT( clk_port   :   IN  STD_LOGIC; 
          test_out_port :   OUT STD_LOGIC);
   END COMPONENT;

   SIGNAL clk_port  :   STD_LOGIC;
   SIGNAL test_out_port :   STD_LOGIC;

BEGIN

   UUT: main PORT MAP(
        clk_port => clk_port, 
        test_out_port => test_out_port
   );

    clk_port_proc : process 
                 begin 
                 clk_port <= '0'; 
                 wait for 10 ns; 
                 clk_port <= '1'; 
                 wait for 10 ns;  
             end process;

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;

这是我的项目结构

但我仍然得到错误的结果。test_out_port 应该随着时钟进程而改变。

我找不到好的教程，所以可能太笨了，但请给我一些帮助

Answer 1

'if' 语句是愚蠢的错误。

if (rising_edge(clk) and tmp_buffer='0') then
        test_out<='1';
        tmp_buffer:='1';

else if (rising_edge(clk) and tmp_buffer='1') then
test_out<='0';
tmp_buffer:='0';
end if;
end if;