vhdl - IEEE Float input to BCD convertion

Question

If i use one std_logic_vector (31 downto 0) as input of my entity. Exists any form of using this 32 bits (IEEE Format) to convert them to ASCII form ?

I have 3.14:

input  ----> 0100 0000 0100 1000 1111 0101 1100 0011 (in IEEE 32 bits form)
output <---- 0011 0011 0010 1110 0011 0001 0011 0100 
               3    3    2    E    3    1    3    4
                \__/      \__/      \__/      \__/
                  3         .         1         4    (in ASCII form)

The number 3.14 is only a example. May be is any number in 32 bits used as input of my entity.