verilog - can iverilog report setup-time violations in Verilog?

Question

I use

specify 
  $setup(d,posedge clk, 5);
endspecify

to give an setup time for dff. However, when clk rises just 2 units of time after d changes, there is not setup time violation issued. I use iverilog to simulate.

How can I see such violations?

Answer 1

看起来你不会看到违规行为。我刚刚下载了我认为是最新的（verilog-0.9.7.tar.gz），我在README.txt文件中看到了这个：

• 指定块被解析但通常被忽略。