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我正在尝试获得两个输出 ( pulse(0) and pulse(1)) 以提供一个短的一个时钟脉冲。这些脉冲之间的延迟需要由一些输入值来控制。所以 0x1 = 1 个时钟周期等。

目前，一旦触发器打开，它就会保持打开状态

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.ipbus.all;

<...snip>


architecture rtl of trig_latency is

signal ack : std_logic;
signal s_level : unsigned(pulse'range);
signal s_level_d1 : std_logic;
signal bit_shift : std_logic_vector(addr_width downto 0);
signal latency: integer:=5;


begin
latency <= to_integer(unsigned(in_data(addr_width -1 downto 0))) when addr_width > 0 else 0;
    process(clk)
        begin
            if rising_edge(clk) then
                if ipbus_in.ipb_strobe='1' and ipbus_in.ipb_write = '1' then
                    s_level <= s_level + 1;
                    s_level_d1<=s_level(s_level'left);
                              else
                               s_level<=(others=>'0);


                end if;

                bit_shift <= bit_shift(bit_shift'high-1 downto 0) & (s_level(s_level'left) and (not s_level_d1));
                ipbus_out.ipb_rdata <= (others => '0');
                ack <= ipbus_in.ipb_strobe and not ack; 

                pulse(0) <= s_level(s_level'left) and (not s_level_d1);
                pulse(1)<=bit_shift(latency);

            end if;

    end process;

  ipbus_out.ipb_ack <= ack;
  ipbus_out.ipb_err <= '0';

end rtl;
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1 回答 1

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为什么你不能完全改变你的位，而忽略它们超出的事实N。通常的 VHDL 移位器使用 将&移位寄存器与新值连接起来：

bit_shift <= bit_shift(bit_shift'high-1 downto 0) & s_level;

那应该可以很好地生成您的移位寄存器。

pulse(1) <= bit_shift(N)应该可以正常工作。

于 2013-09-18T12:36:07.233 回答