我正在尝试为模块的基本结构编写verilog代码，rsa cryptosystem如下所示。
尽管代码在模拟中运行良好，但会发出警告：
Xst:1710 - FF/Latch <out_en> (without init value) has a constant value of 1 in block <o1>. This FF/Latch will be trimmed during the optimization process.
and Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aa_1> (without init value) has a constant value of 0 in block <test1>. This FF/Latch will be trimmed during the optimization process.
我正在使用赛灵思 ise 13.1。
请帮我
module okletssee(
input en,
input clk,
input[2:0] a,b,
output reg[2:0] c,
output reg out_en
);
always @(posedge clk)
begin
if(en==1'b1)
begin
c=a+b;
out_en=1'b1;
end
else out_en=1'b0;
end
endmodule
module test1(
input[2:0] a,b,
input clk,
output reg[2:0] out_reg
);
wire[2:0] cc;
wire out1_en;
reg[2:0] aa,bb;
reg en;
okletssee o1(en,clk,aa,bb,cc,out1_en);
reg cse;
always @(posedge clk)
begin
case(cse)
default: begin
aa=a;
bb=b;
en=1'b1;
cse=1'b1;
end
1'b1: begin
if(out1_en==1'b1)
out_reg=cc;
else cse=1'b1;
end
endcase
end
endmodule