hardware - a <= a + 1 是 VHDL 中的一个好习惯吗？

Question

如果我在 VHDL 过程中编写将 a 分配为 a+1 的语句，这是一个好习惯吗？

我对此感到困惑，因为模拟器工作正常，但是当我尝试在 FPGA 中实现它时，综合工具会抱怨创建锁存器。

这是什么意思？

Answer 1

你应该只在时钟进程中做这样的声明。如果您想对其进行综合，建议进行额外的初始化（重置）。可能如下所示：

process(clk, reset)
begin
   if reset='1' then
      a <= 0;
   elsif rising_edge(clk) then
      a <= a + 1;
   end if;
end process;

Answer 2

在时钟过程中，这很好。其他地方，可能不会。

Answer 3

Do it in a clocked process, that's fine. What it means is "the next value of a should be the current value of a +1"

---

If you do it as a continuous assignment (outside of any process), what you are saying is "a is always getting a+1 assigned to it" which is a self-referential loop!

If you include a in the sensitivity list of an enabled process, you get the same effect

process (en, a)
begin
   if en = '1' then 
      a <= a + 1;
   end if;
end process;

(You can use this form to create transparent latches:

process (en, insig)
begin
   if en = '1' then 
      a <= insig;
   end if;
end process;

)

---

If you do it in a non-clocked process, which is not sensitive to a:

process (en)
begin
   if en = '1' then 
      a <= a + 1;
   end if;
end process;

You will create a positive-edge-triggered latch, as a needs to keep its value between changes of en. Effectively, en becomes a clock to a d-type flipflop.